Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques signatures have been applied to protect authenticate relevant information. However, with advent of quantum computers algorithms, classical cryptographic danger collapsing because can solve complex problems polynomial time. Stemming from that risk, researchers worldwide stepped up research on post-quantum algorithms resist attack by computers. In this review paper, we survey...

The efficiency of polynomial multiplication execution majorly impacts the performance lattice-based post-quantum cryptosystems. In this research, we propose a high-speed hardware architecture to accelerate based on Number Theoretic Transform (NTT) in CRYSTAL-Kyber and CRYSTAL-Dilithium. We design Digital Signal Processing (DSP) for modular butterfly Point-Wise Multiplication (PWM) operations. Our method reduces critical path delay an n-bit multiplier that (2n-2)-bit adder, optimizing both...

A Trusted Execution Environment (TEE) sets a platform to secure applications based on the Chain-of-Trust (CoT). The starting point of CoT is called Root-of-Trust (RoT). However, RoT implementation often relies obscurity and provides little flexibility when generating keys system. In this paper, TEE System-on-a-Chip (SoC) architecture proposed heterogeneous design by combining 64-bit Linux-capable processors with 32-bit Micro-Controller Unit (MCU). built cores, while MCU takes care sensitive...

Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced TLS 1.3, mitigating the sidechannel attacks suites based on Advanced Encryption Standard (AES). However, few implementations cannot provide sufficient speed compared to other encryption standards with Authenticated Associated Data (AEAD). This paper shows ChaCha20 and Poly1305 primitives. In addition, compatible AEAD 1.3 implemented...

All cryptography systems have a True Random Number Generator (TRNG). In the process of validating, these are necessary for prototyping in Field Programmable Gate Array (FPGA). However, TRNG uses an entropy source based on non-deterministic effects challenging to replicate FPGA. This work shows problems and solutions implement frequency collapse multimodal Ring Oscillators (RO). The implemented FPGA pass all SP800-90B tests from National Institute Standards Technology (NIST) with good...

Substitution boxes (S-Boxes) function as essential nonlinear elements in contemporary cryptographic systems, offering robust protection against cryptanalytic attacks. This study presents a novel technique for generating compact 8-bit S-Boxes based on multiplication the Galois Field GF(24). The goal of this method is to create with low hardware implementation cost while ensuring properties. Experimental results indicate that suggested achieve nonlinearity value 112, matching AES S-Box. They...

Despite being proposed since more than 50 years ago, COordinate Rotation DIgital Computer (CORDIC) is still one of the most effective algorithms for elementary function calculation so far. Original CORDIC, however, suffers high latency due to its nature unvarying number rotations. As a result, low-latency hybrid adaptive (HA) CORDIC in this paper. Firstly, angle selection decreases total iterations up 50% with respect higher accuracy results. Secondly, architecture including fixed-point...

The Number Theoretic Transform (NTT) has been widely used to speed up polynomial multiplication in lattice-based post-quantum algorithms. All NTT operands use modular arithmetic, especially multiplication, which significantly influences hardware implementation efficiency. Until now, most implementations Digital Signal Processing (DSP) multiply two integers and optimally perform modulo computations from the product. This paper presents a customized Lattice-DSP (L-DSP) for based on Karatsuba...

The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, image processing cores, etc. In this paper, design unsigned 32-bit is proposed, aiming to achieve best timing performance with an appropriate area. proposed architecture consists modified Radix-4 Booth encoder, Wallace Tree adder, Carry Look Ahead adder. has been verified successfully on DE2-115 then synthesized ASIC implementation. FPGA-based experimental result shows that...

Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive numerous research. In this paper, low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks logic elements, 50-MHz DBP capable performing 1,024 queries for entire 32,768 4-KB records within around...

The Trusted Execution Environment (TEE) offers a software platform for secure applications. TEE memory isolation scheme and authentication from high privilege mode. procedure uses different algorithms such as hashes signatures, to authenticate the application secure. Although hardware has been defined isolation, security often are executed using implementations. In this paper, RISC-V system compatible with TEEs featuring algorithm accelerators is presented. SHA-3 hash Ed25519 elliptic curve...

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI to be optimized low power consumption or high performance proper biases, depending on the required application. This article proposes using biasing technique in novel countermeasures against analysis attacks. Theoretical explanations are discussed, and realistic differential (DPA) attacks, targeting AES-128 encryption a 65-nm STOB 32-bit...

The IoT applications use embedded processors to execute lightweight tasks for sensing and management of communications, using different energy harvesting strategies. However, many need a low-power consumption the limitation power supplies. This paper presents low-area System On Chip (SoC) with stable supply. SoC consists microprocessor, 1-KB Static Random Access Memory (SRAM), debug module, timer, General-Purpose In-Outs (GPIO), Serial Peripheral Interface (SPI) programmer. processor uses...

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays essential role in many security applications, such as transport layer (TLS), internet protocol (IPsec), wireless sensor networks (WSNs). The proposed designs of hardware implementation only focus on a single variant use resources. These proposals cannot be used for resource-constrained applications or the devices that need provide...

Physical cryptographic devices are vulnerable to side-channel information leakages during operation. They widely used in software as well hardware implementations, ranging from microcontrollers and microprocessors accelerators System on Chips (SoCs). Nowadays, RISC-V SoCs becoming the most prominent solution compared rest. Cryptographic provide users with a very high level of flexibility customization chips suited specific applications these systems. First, this research aims confirm...

Bitmap index is recognized as a promising candidate for online analytics processing systems, because it effectively supports not only parallel but also complex and multi-dimensional queries. However, bitmap creation time-consuming task. In this study, by taking full advantage of massive computing field-programmable gate array (FPGA), two hardware accelerators creation, namely BIC64K8 BIC32K16, are originally proposed. Each the accelerator contains primary components, an enhanced...

True Random Number Generator (TRNG) is used in many applications, generally for generating random cryptography keys. In this way, the trust of system depends on quality numbers generated. However, entropy fluctuations produced by external perturbations generate some false positives sequence. These can a disastrous scenario, depending application. This work presents results different tests to demonstrate robustness and health TRNG based frequency collapse. The passed all provided NIST...

Today, Hash-based Message Authentication Code with Secure Hash Algorithm 2 (HMAC-SHA2) is widely used in modern protocols, such as Internet Protocol Security (IPSec) and Transport Layer (TLS). Many authors proposed their HMAC-SHA2 hardware implementations. Some targeted a high-performance design, while others aimed to satisfy an area constraint. Those implementations are acceptable for applications that require only low-cost or high throughput. However, some applications, Software-Defined...

Despite the impressive search rate of one key per clock cycle, update stage a random-access-memory-based content-addressable-memory (RAM-based CAM) always suffers high latency. Two primary causes such latency include: 1) compulsory erasing along with writing and 2) major difference in data width between RAM-based CAM (e.g., 8-bit width) modern systems 256-bit width). This brief, therefore, proposes an efficient input/output (I/O) architecture binary (RCAM) for low-latency update. To achieve...

With the rising data evolution, demand for secured communications over networks is immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill requirements of modern network applications. Many proposals published year different variants ECC satisfied some issues. Nevertheless, applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put on various aspects can only be solved by algorithms. Looking at this point view, efficient architecture...