Substitution boxes (S-Boxes) function as essential nonlinear elements in contemporary cryptographic systems, offering robust protection against cryptanalytic attacks. This study presents a novel technique for generating compact 8-bit S-Boxes based on multiplication the Galois Field GF(24). The goal of this method is to create with low hardware implementation cost while ensuring properties. Experimental results indicate that suggested achieve nonlinearity value 112, matching AES S-Box. They...

Wireless sensor network (WSN) has emerged as a significant application among Internet-of-Things (IoT) applications. Energy harvesting systems have high potential for deployment in WSN to monitor natural environments and industrial equipment. With limited resources, including power chip area, an energy system demands thorough resource allocation several circuits like control system, sensors, transceiver. Also, such are required function with low-peak adapt the fluctuation of harvested energy....

Internet-of-things networks consist of multiple sensor devices spread over a wide area. In order to protect the data from unauthorized access and tampering, it is essential ensure secure communication between central server. This security measure aims guarantee authenticity, confidentiality, integrity. Unlike traditional computing systems, node are often limited regarding memory power. Lightweight protocols, such as LoRaWAN, were introduced overcome these limitations. However, despite...

This work presents a 32-bit Reduced Instruction Set Computer fifth-generation (RISC-V) microprocessor with COordinate Rotation DIgital (CORDIC) accelerator. The accelerator is implemented inside the core and being used by software via custom instruction. VexRiscv Architecture (ISA) of RV32IM; that means RISC-V including Integer Multiplication. experimental results were collected using Field-Programmable Gate Array (FPGA) on DE2-115 development kit Application Specific Integrated Chip (ASIC)...

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms speed and side-channel resistance compared software implementations. In addition, a hardware implementation can provide the possibility unifying functionality with some secure primitive, for example, true random number generator (TRNG) or physical unclonable function (PUF). This paper presents unified PUF-ChaCha20 field-programmable gate-array (FPGA) implementation. The problems...

Hardware security primitives provide Root-of-Trust (RoT) procedures for booting, authentication, and key generation processes in secure integrated systems. The RoT requires True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs), non-volatile memories essential identity authentication. However, these implementations introduce challenges due to the physical phenomena used each primitive, requiring complex calibration or special technologies with additional masks. In...

In this paper, a 32-bit RISC-V microcontroller in 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system developed based on the VexRiscv Central Processing Unit (CPU) with Instruction Set Architecture (ISA) extensions of RV32IM. Besides core processor, System-on-Chip (SoC) contains 8KB boot ROM, 64KB on-chip memory, UART controller, SPI timer, and GPIOs for LEDs switches. ROM has 7KB hard-code combinational logics 1KB stack SRAM. proposed SoC performs Dhrystone Coremark benchmarks...

A Physical Unclonable Function (PUF) exploits uncontrollable variations in manufacturing to characterize an integrated circuit. There have been many PUF designs proposed which apply different strategies extract process variation on Field Programmable Gate Arrays (FPGAs). Ring Oscillator (RO PUF) is one of the FPGA-friendly taking advantage difference hardware delay generate unpredictable output a silicon device. This paper proposes novel RO FPGA based feedforward ring oscillators (FRO). The...

Fronthaul is associated with a new and different type of Radio Access Network architecture consisting centralized Baseband Units (BBUs) Remote (RRUs) [2] . In order to meet the fifth-generation wireless (5G) challenges increased traffic data flows, connection protocol for fronthaul network called Evolved Common Public Interface (eCPRI) has been published. This paper aims design system that supports this interface transmit from BBUs RRUs in 5G (RAN). By referencing specification eCPRI, we...

The Trusted Execution Environment (TEE) is designed to establish a safe environment that prevents the execution of unauthenticated programs. nature TEE continuous verification process with hashing, signing, and verifying. Such called Chain-of-Trust, derived from Root-of-Trust (RoT). Typically, RoT pre-programmed, hard-coded, or embedded in hardware, which locally produced checked before booting. employs various cryptographic processes throughout boot verify authenticity bootloader. It also...

Full-text search has a wide range of applications, including tracking systems, computer vision, and natural language processing. Standard methods usually implement two-phase procedure: indexing retrieving, with the retrieval performance entirely dependent on index efficiency. In most cases, more powerful algorithm, memory processing time are required. The amount required to collection documents is proportional its overall size. this paper, we propose full-text hardware implementation without...

This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with COordinate Rotation DIgital (CORDIC) algorithm accelerator. The implemented core processor is the VexRiscv CPU, an RV32IM variant of RISC-V ISA processor. Within core, CORDIC accelerator was connected directly to Execute stage. placed in Briey System-on-Chip (SoC) and synthesized on Field Programmable Gate Array (FPGA) Application Specific Integrated Chip (ASIC) level cell logic ROHM- 180nm technology

In the age of computer evolution, number data grows swiftly. Moreover, requirement extracting information from database becomes urgent. Full-text search provides methods to quickly locate multiple keywords inside extensive text and has gained more consideration in recent years. The proposed tools, such as Lucene, Hyper Estraier, Namazu, are based on general-purpose processors. They spend time index input documents require space store these indexes. this work, we provide a processor design...

In an Internet of Things (IoT) system, many embedded devices are deployed to gather massive amounts information. These may collect indexes natural substances (air, soil, water) or physiological parameters provide data for later assessment on environmental conditions improving healthcare. Gathering this information requires processors execute lightweight tasks involving sensing and communication through a wireless channel. This paper presents low-area System Chip (SoC) capable performing IoT...

Deep Learning (DL) training process involves intensive computations that require a large number of memory accesses. There are many surveys on behaviors with the DL training. They use well-known profiling tools or improving existing to monitor processes. This paper presents new approach profile using co-operate solution from software and hardware. The idea is Field-Programmable-Gate-Array as main for processes computer. Then, both hardware point-of-views can be monitored evaluated. most...