A5074190672- Physical Unclonable Functions (PUFs) and Hardware Security
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Analog and Mixed-Signal Circuit Design
- Neuroscience and Neural Engineering
- Integrated Circuits and Semiconductor Failure Analysis
- Chaos-based Image/Signal Encryption
- Cryptographic Implementations and Security
- Human Pose and Action Recognition
- Neural Networks and Applications
- Computer Graphics and Visualization Techniques
- Interconnection Networks and Systems
- Network Time Synchronization Technologies
- Robotics and Sensor-Based Localization
- Advanced Data Storage Technologies
- Parallel Computing and Optimization Techniques
- Electrostatic Discharge in Electronics
- Network Traffic and Congestion Control
- Algorithms and Data Compression
- Speech Recognition and Synthesis
- Wireless Networks and Protocols
- Advanced Malware Detection Techniques
- Advanced Data Compression Techniques
META Health
2025
University of Waterloo
2021-2022
University of Rio Grande and Rio Grande Community College
2013
Universidade Federal do Rio Grande do Sul
2011-2013
Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional countermeasures have a limited scope protection and impose several restrictions on how sensitive data must manipulated. We demonstrate bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software run little to countermeasures, reducing code size performance overheads. Unlike previous literature, our...
This work proposes a strategy for designing VLSI circuits to operate in an extremely wide Voltage-Frequency Scaling (VFS) range, from the supply voltage at which minimum energy per operation (MEP) is achieved, up nominal process. First sizing methodology of two library cells using transistors with different threshold voltages: Regular-VT (RVT) and Low-VT (LVT) described. Just five combinational cells: INV, NAND, NOR, OAI21, AOI22 comprise libraries plus register cells, all multiple...
This paper presents results of digital CMOS design for ultra-low power filter that uses logic cells operating at near-threshold voltage supplies. The were designed in 65 nm technology power. hardware implementation a pole-radius-varying Infinite Impulse Response (IIR) notch is addressed. Previous works have shown (or Q factor-varying) IIR filters can suppress the transient effect. proposed synthesized using our custom standard library. Comparisons from operation to nominal voltages show...
OWD is becoming increasingly important nowadays, as SLA agreements use it a parameter to ensure QoS levels. However, its measurement still much debated topic due the difficulty in clock synchronization process. The paper approaches new methodology measure OWD, using NTP protocol with virtual clocks and bigger packets. This approach works over tool developed by authors, called Netmetric, flexible enough be applied full-mesh networks, without lack consistency during concurrent...
Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This paper shows that it possible achieve 8x higher energy-efficiency with a very-wide range dynamic voltage-frequency scaling, from nominal voltages down lower boundary near-VT operation. The cell-library exercised in 65nm commercial PDK targets operation, mitigating effects without compromising design terms area energy at strong inversion. set...
Strong physical unclonable functions (PUFs) provide a low-cost authentication primitive for resource-constrained devices. However, most strong PUF architectures can be modeled through learning algorithms with limited number of CRPs. In this article, we introduce the concept nonmonotonic response quantization PUFs. Responses depend not only on which path is faster but also distance between arriving signals. Our experiments show that resulting has increased security against attacks. To...
Low-Latency and Low-Power Edge AI is essential for Virtual Reality Augmented applications. Recent advances show that hybrid models, combining convolution layers (CNN) transformers (ViT), often achieve superior accuracy/performance tradeoff on various computer vision machine learning (ML) tasks. However, ML models can pose system challenges latency energy-efficiency due to their diverse nature in dataflow memory access patterns. In this work, we leverage the architecture heterogeneity from...
With the emergence of Metaverse and focus on wearable devices in recent years gesture based human-computer interaction has gained significance. To enable recognition for VR/AR headsets glasses several datasets focusing egocentric i.e. first-person view have emerged years. However, standard frame-based vision suffers from limitations data bandwidth requirements as well ability to capture fast motions. overcome these limitation bio-inspired approaches such event-based cameras present an...
Flip-flops are a key component of digital integrated circuits and substantially affect their power energy consumption. In this paper, an ultra low-power, contention-free, static single-phase 3-transistors clock load flip-flop is described referred to as 19-T Ultra Low-power Flip-flop (ULFF). Simulation results in CMOS 65 nm technology show that at nominal conditions Data Activity (DA) 10%, the ULFF has 56% 7% low-power consumption compared 18-T Single-phase Clocked Static (18TSPC),...
Strong physical unclonable functions (PUFs) provide a low-cost authentication primitive for resource constrained devices. However, most strong PUF architectures can be modeled through learning algorithms with limited number of CRPs. In this paper, we introduce the concept non-monotonic response quantization PUFs. Responses depend not only on which path is faster, but also distance between arriving signals. Our experiments show that resulting has increased security against attacks. To...
Strong PUFs provide low-cost authentication primitive for resource constrained devices. They use inherent process variation as basis to generate a unique fingerprint, which often lacks the required reliability. Environmental factors, and time varying aging mechanisms can further compromise In this paper, we investigate impact of power supply voltage temperature screens improve strong PUF performance metrics. Our simulation measurement results in 65 nm show reliability 97.4% when operating at...
Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional counter-measures have limited scope protection, and impose several restrictions on how sensitive data must manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software run little to counter-measures, reducing code size performance overheads. Unlike previous literature, our...
We design, implement, and assess the security of several variations PUF-on-PUF (POP) architecture. perform extensive experiments with deep neural networks (DNNs), showing results that endorse its resilience to learning attacks when using APUFs 6, or more, stages in first layer. Compositions 2, 4 are shown vulnerable DNN attacks. reflect on such results, extending previous techniques influential bits stage bias APUF instances. Our data shows compositions not always preserve properties PUFs,...
We propose a secure and lightweight key based challenge obfuscation for strong PUFs. Our architecture is designed to be resilient against learning attacks. mechanism uses non-linear feedback shift registers (NLFSRs). Responses are directly provided the user, without error correction or extra post-processing steps. also discuss cost of protecting our power analysis attacks with clock randomization, Boolean masking. Security assessed using avalanche criterion, deep-neural network testchip in...
The Burrows-Wheeler transform (BWT) is used by the bzip2 family of compressors. In this paper, we present a hardware architecture that implements an inplace algorithm to compute BWT. Our design does not have explicit storage for suffix array, or output array. performance our implementation fixed, and depend on input string content. We use register based character buffer in scanchain configuration, such BWT computed from right left, as characters are loaded. Loading new done every six cycles,...