A5048803081- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Thin-Film Transistor Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Silicon and Solar Cell Technologies
- Low-power high-performance VLSI design
- Silicon Nanostructures and Photoluminescence
- Ferroelectric and Negative Capacitance Devices
- Nanowire Synthesis and Applications
- Analog and Mixed-Signal Circuit Design
- Advanced Surface Polishing Techniques
- Semiconductor Quantum Structures and Devices
- Advanced Data Storage Technologies
- Mechanical and Optical Resonators
- Advanced MEMS and NEMS Technologies
- Electronic and Structural Properties of Oxides
- Cellular Automata and Applications
- Photonic and Optical Devices
- Acoustic Wave Resonator Technologies
- Advanced Sensor Technologies Research
- Interconnection Networks and Systems
- solar cell performance optimization
- CCD and CMOS Imaging Sensors
- Advanced Research in Systems and Signal Processing
Intel (United States)
2016-2023
Mission College
2016
Cypress Semiconductor Corporation (United States)
2015
IBM (United States)
2006-2014
GlobalFoundries (United States)
2014
IBM Research - Austin
2014
IBM Research - Thomas J. Watson Research Center
2012
Massachusetts Institute of Technology
2001-2011
Integrated Device Technology (United States)
2011
University of Tehran
2000-2006
A simple semiempirical model I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> (V xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> , V xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) for short-channel MOSFETs applicable in all regions of device operation is presented. The based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as ldquovirtual sourcerdquo (VS) model. simplicity comes from fact that...
A simple model that links MOSFET performance, in the form of intrinsic switch delay, to effective carrier velocity channel is developed and fitted historical data. It shown nearly continuous increase, most recently via introduction process-induced strain, has been responsible for device performance increase commensurately with dimensional scaling. The paper further examines material innovations will be required order maintain continued commensurate scaling beyond what can achieved discusses...
A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used derive a new formulation of the intrinsic switching delay transistor. The proposed follows scaling trend experimental ring-oscillator data better than conventional <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i> / xmlns:xlink="http://www.w3.org/1999/xlink">I</i> metric. historical performance examined, and it shown...
We present a new ETSOI CMOS integration scheme. The process flow incorporates all benefits from our previous unipolar work. Only single mask level is required to form raised source/drain (RSD) and extensions for both NFET PFET. Another feature of this work the incorporation two strain techniques boost performance, (1) Si:C RSD SiGe PFET, (2) enhanced stress liner effect coupling with faceted RSD. Using boosters we demonstrate PFET drive currents 640 490 ¿A/¿m, respectively, at I <sub...
We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) of 20nm BOX thickness (T xmlns:xlink="http://www.w3.org/1999/xlink">BOX</sub> 25nm, featuring dual channel FETs (Si NFET compressively strained SiGe PFET). Competitive effective current (I xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> reaches 630μA/μm 670μA/μm PFET,...
Carrier velocity in the MOSFET channel at top of barrier near source (virtual source) is main driving force for improved transistor performance with scaling. This paper uses an analytical model that relates intrinsic delay to key technology parameters and presents a methodology extracting those from literature benchmark papers. A historical trend including most recent results strain engineering presented extrapolated what required order scaling continue. Key findings their theoretical...
We present UTBB devices with a gate length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal raised source/drains (RSD). Back bias (V xmlns:xlink="http://www.w3.org/1999/xlink">bb</inf> enables V xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> modulation more than 125mV 0.9V BOX thickness 12nm. This demonstrates the importance...
For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record speed ring oscillator (fan-out = 3) delay of 8.5 ps/stage and 11.2 V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> 0.9V 0.7V, respectively, outperforming state-of-the-art finFET results. A novel "STI-last" integration scheme is developed to improve...
Metal-oxide-semiconductor field effect transistors (MOSFET) with a thin high-k dielectric were fabricated on bulk n-type germanium substrates. Surface oxides thermally desorbed in situ by heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was formed evaporating presence of atomic oxygen and nitrogen supplied from remote radio frequency plasma source. Subsequently, HfO2 deposited hafnium oxygen. An TaN metal gate similarly deposited. Long channel...
The analytical MOSFET intrinsic delay introduced in Part I of this paper is used to examine the tradeoffs between key device elements required order for performance scaling trend continue future high-performance CMOS generations. A scenario based on contacted source/drain gate pitch presented and prospects nodes. It shown that, from 32-nm node onwards, will counterscale, mainly due increase parasitic capacitance as a result proximity electrodes. As case study, dependence transistor various...
We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by deepest trenches, this architecture enables a full use of back bias while staying compatible with both standard bulk design conventional SOI substrates. demonstrate 20nm ground rules that we able to tune V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Prospects of velocity enhancement as the main driver performance scaling in future CMOS are examined. Limits uniaxially strained Si first presented and then outlooks novel channel materials such Ge III-V semiconductors discussed. Finally, characteristics under power dissipation constraints studied.
Continued improvement in the 3D NAND bit density is essential to satisfy exponentially growing demand for data storage. The transition from 3b/cell (TLC) 4b/cell (QLC) a significant step towards delivering higher density. increased program/erase (P/E) window, technology, combined with improved program algorithms alleviate interference neighboring WL cells, has led successful deployment of two generations QLC floating gate (FG) technology [1]. Further density, as well read and write...
Successful deployment of multiple generations the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\mathsf{b}/\mathsf{cell}$</tex> (QLC) floating-gate 3D-NAND technology has paved way for industry-wide adoption xmlns:xlink="http://www.w3.org/1999/xlink">$\mathsf{QLC} [1-4]$</tex> . The transition to 5b/cell (PLC) will be another steppingstone accelerating bit density growth and expanding Flash storage wider markets, where a lower cost at...
We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, demonstrate that all devices including analog, I/O, passive can be fabricated in the silicon layer. Excellent device matching, g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> scaling to small gate length, good RF performance, absence history effect are main...
We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted pitch of 100 nm. At an effective length 18 drain-induced barrier lowering mV is achieved by either thinning the nm or applying reverse back-gate bias 6-nm MOSFETs. Moreover, minimal increase in series resistance seen when scaled resulting no performance degradation scaling.
High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) PFET examined. Significant performance is demonstrated with competitive drive currents of 1.65mA/µm 1.25mA/µm, I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> 0.95mA/µm 0.70mA/µm at xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> =100nA/µm V...
UTBB FDSOI technology is a faster, cooler and simpler addressing the performance/energy consumption trade-off. In this paper we present main front-end-of-the-line knobs to scale down promising 10nm node.
For the first time, we report fabrication and characterization of high-performance s-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization s-SiGe fins W xmlns:xlink="http://www.w3.org/1999/xlink">FIN</sub> =3.3nm devices L xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =16nm, in a CMOS...
Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e., <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ~ 25 nm a contacted pitch of 130 nm) were fabricated using gate-first flow. A “long narrow” fin layout length 1 μm) was leveraged to preserve uniaxial tensile strain in...
Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption mainstream CMOS. This especially true low-power applications, where wafer cost deemed significantly add the total cost. We recently reported novel scheme overcome some major manufacturing issues such as difficulty in doping silicon layer, process induced loss,...
We present, for the first time, mechanically-flexible advanced-node CMOS circuits, including SRAM and ring oscillators, with gate lengths <;30 nm contacted pitch of 100 nm. Our novel layer transfer technique called "controlled spalling" is employed as an incredibly simple, low-cost, manufacturable approach to separate finished circuits from host silicon substrate. The overall performance flexible devices are carefully examined, demonstrating functional cells down V <sub...