A5087824169- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- GaN-based semiconductor devices and materials
- Electronic and Structural Properties of Oxides
- Semiconductor Quantum Structures and Devices
- Ga2O3 and related materials
- Nanowire Synthesis and Applications
- Electrostatic Discharge in Electronics
- Copper Interconnects and Reliability
- Metal and Thin Film Mechanics
- Silicon Carbide Semiconductor Technologies
- Photonic and Optical Devices
- Advanced Memory and Neural Computing
- Gas Sensing Nanomaterials and Sensors
- Radio Frequency Integrated Circuit Design
- Catalysis for Biomass Conversion
- ZnO doping and properties
- Plasma Diagnostics and Applications
- Membrane-based Ion Separation Techniques
- Catalysis and Hydrodesulfurization Studies
- Semiconductor materials and interfaces
- Advancements in Photolithography Techniques
- Chalcogenide Semiconductor Thin Films
University of Virginia
2024
CEA LETI
2011-2023
CEA Grenoble
2012-2023
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2014-2023
Institut polytechnique de Grenoble
2011-2023
Université Grenoble Alpes
2011-2023
IFP Énergies nouvelles
2018
Direction de la Recherche Technologique
1993-2014
STMicroelectronics (France)
2003-2006
PSA Peugeot Citroën (France)
2005
An original technique for the dynamic analysis of Id(Vg) hysteresis on high K stacks is proposed, allowing characterization Vt shift transients at short times. The experimental results demonstrate that trapping/de-trapping mechanism by tunneling from substrate must be considered. Furthermore, a new model based trap-like approach successfully developed to interpret dependence phenomena with k gate stack architecture.
The apparent kinetics in metal/acid bifunctional catalysis is generally strongly affected by the metal to acid site ratio and their proximity. However, these two key parameters have not been systematically investigated scientific literature. Such a study provided here for catalysts using platinum as metallic function EU-1 zeolite acidic function. Two series of with different sites ratios distances were prepared tested ethylcyclohexane hydroconversion. By increasing ratio, catalytic activity...
An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 EOT. Detailed characterisation (TEM, C-V, split charge pumping, LF noise, low and high temperature transport) demonstrate the quality of dielectric interface. Low Ioff current make technology attractive for standby power applications.
A time-resolved analysis of the capacitance–voltage (C–V) technique and an inverse modeling approach have been developed to determine energy distribution capture cross section interface traps in silicon band gap from multifrequency C–V measurements. In this work, our method is performed on n-type metal-oxide-semiconductor capacitors with HfSixOy/HfO2 gate dielectric stack polysilicon gate. From frequency dispersion data, we evidence a peak acceptor states upper half at 0.81 eV above valence...
For the first time, we demonstrate low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (V xmlns:xlink="http://www.w3.org/1999/xlink">Tlin</sub> ±0.32V) nMOS and pMOS adjusted in a gate FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune above midgap while maintaining good reliability...
We report the fabrication and characterization of chemical vapor deposition (CVD) grown silicon nanowires capacitors using a complementary-metal-oxide-semiconductor (CMOS) circuit interconnect level compatible process. Silicon have been by CVD on metallic lines used in today's CMOS circuits at low temperature (<425 °C) copper as catalyst. The nanowire assembly develops huge surface leading to very high measured capacitance densities reaching 18 μF/cm2, featuring ×23 gain when compared same...
The presence of an ultrathin oxide layer at the high-k/SiO2 interface may result in interfacial dipole related to specific high-k dielectric used for gate stacks. 1 nm HfO2/x nmAl2O3/SiO2/Si stacks with different x values (x=0, 0.4, 0.8, 1.2) have been prepared by atomic deposition. Using photoelectron spectroscopy, Al-related HfO2/Al2O3/SiO2 stack has identified. X-ray spectroscopy analysis shows that is correlated formation Al-silicate. located Al-silicate between Al2O3 and SiO2, its...
The III–V materials offer superior optoelectronic performance that makes them an attractive choice for integration into cheap and ubiquitous Si-based technologies, contingent upon addressing the consequences of prohibitively large lattice constant mismatch between two material systems. We present a near-infrared (NIR) resonant cavity-enhanced photodetector (RCE PD) monolithically integrated onto nominal Si(001) substrate incorporating thin InGaAs/GaAsP strained-layer superlattice acting as...
We study the effective metal gate work function (WF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Meff</sub> ) of different metal/high-κ stacks. Both capacitance versus voltage measurement and internal photo emission were used, leading to a better understanding WF variations. demonstrate that these variations are related two main process dependent parameters, drop at high- κ/SiO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface...
We study the electro optical properties of a Metal-Nitride-Oxide-Silicon (MNOS) stack for use in CMOS compatible plasmonic active devices. show that insertion an ultrathin stoichiometric Si(3)N(4) layer MOS lead to increase electrical reliability copper gate MNOS capacitance from 50 95% thanks diffusion barrier effect, while preserving low losses brought by as plasmon supporting metal. An experimental investigation is undertaken at wafer scale using some standard processes LETI foundry....
This work focuses on interconnect heating during fast ESD transients. A simplified thermal RC network is used to study the behavior of interconnects and predict their failures, which can be an open circuit or a latent failure due decrease in electromigration lifetime. The model validated by both experiments finite difference simulations. We observe that melting system considered instantaneous. Simulations solid liquid phases metal are good agreement with experiments. Human body (HBM) machine...
An analytic electrical model for accurate capacitance-voltage (C-V) characterization of high- gate dielectrics using a mercury probe is presented. This approach considers the series association dielectric/substrate impedance, circuit resistance, and an additional impedance modeling interfacial layer between oxide mercury-drop contact. useful to describe frequency behavior C-V measurements in wide range frequencies (500 Hz 100 kHz). The extraction procedure parameters described method...
Voltage drop induced by an electrical dipole layer after the incorporation of La or Al in high-k/metal gate-stack has been measured on nominal and beveled-SiOx devices linearly correlated to effective La/Al dose into high-k/SiOx stack determined through X-ray fluorescence spectroscopy. Electrical dipoles were experimentally estimated be around -55 +40 meV for each 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> at/cm...
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads an improvement gate stack reliability below 525°C (iii) state-of-the-art SiOCH ULK iBEOL up 550°C 5h W metal lines. A integration thus proposed match the windows of bottom...
We demonstrate by an extensive experimental study of HfO/sub 2//TiN and SiO/sub gate stacked-transistors compared with the 2//poly-Si reference, that hole mobility is mainly degraded surface roughness (SR) linked to presence TiN. thus propose high SiGe or SiGe:C channel pMOSFETs stacks using adequate valence band engineering near dielectric/channel interface (up 100% enhancement at E/sub eff/ = 1 MV/cm). On other hand, electron reduced remote Coulomb scattering (RCS).