The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets data. More recent computing paradigms, such as high parallelization near‐memory computing, help alleviate data bottleneck to some extent, but paradigm‐shifting concepts are required. In‐memory has emerged a prime candidate eliminate this by colocating processing. In context, resistive switching...

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities brain, may provide such shift. Many researchers across academia industry have been studying materials, devices, circuits, systems, implement some functions networks neurons synapses develop...

This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the network calibration utilizes trainable memristor weight to adapt device mismatch increase Rather than conventional binary searching, we adopt quaternary searching in ADC realize architecture's coarse fine bits determination. A level-crossing is...

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors also applied in logic circuit design. Material implication is one of the main areas with memristors. In this paper optimized full adder design by material presented. This needs 27 less area comparison typical CMOS-based 8-bit adders. Also presented only 184 computational steps which enhance former speed 20 percent.

During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal-Oxide-Semiconductor (CMOS), in power area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose novel low-latency parallel Convolutional Neural Network (CNN) architecture...

Neuromorphic Computing In article number 1900189, Mostafa Rahimi Azghadi, Yao-Feng Chang, and co-workers discuss challenges opportunities shed light on recent advances in CMOS, SiOx-based memristive, mixed CMOS-memristive hardware for neuromorphic systems. New published results are provided from various devices that developed to replicate selected functions of neurons, synapses, simple spiking networks, which used MNIST pattern classification.

Memristor as an emerging history dependent nanometer scaled element will play important role in future nanoelectronic computing technologies. Some pure and hybrid memristor-based implementation techniques have been proposed recent years. Material implication logic is one of the significant areas for implementation. In this paper a linear feedback shift register implemented based on material logic. It by 8 memristors which considerably used less area comparison with conventional CMOS-based...

Memristor is considered as one of the promising solutions to fundamental limitations VLSI systems. Logic implementation with memristor device by considering its compatibility CMOS fabric provides a new vision for digital logic circuits. This work presents 2 multiplier cell design using hybrid CMOS-memristor universal gate. The gate based approach extension ratioed (MRL) lower cost. Simulation results confirm functionality proposed circuit. circuit requires 16 memristors, 8 transistors and...

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M architecture, capable memory logic applications, based on transistor-less cell, which behaves switching circuit. The proposed cell consists two access target memristors that utilize gating structure by devices to reduce sneak path effect. has considerably lower wiring density number per bit compared with its peers....

In this paper, design of a passive resistive-type neuron is proposed to generate the hyperbolic tangent function as activation function. The has advantage not needing any biasing voltage and therefore its power consumption low. circuit designed simulated in 180 nm CMOS technology. shows good approximation with maximum error average from ideal by 19.7% 6.88% respectively. 62.5 μW while standby zero. Also applied large neural network results functionality. pattern recognition implemented using...

This brief presents a hybrid CMOS-memristor logic design and implementation method on novel mirrored crossbar architecture. The proposed structure supports in-memory computation needs only one computational step to perform basic Boolean expressions. can provide multiple fanins and/or fanouts, does not have destructive effect input devices' logical states. Various gates been designed using the structure. Simulation results practical constraints for different functions are presented, which...

We present a novel cryptography architecture based on memristor crossbar array, binary hypervectors, and neural network. Utilizing the stochastic unclonable nature of error tolerance hypervectors network, implementation algorithm simulation is made possible. demonstrate that with an increasing dimension nonidealities in circuit can be effectively controlled. At fine level controlled non-ideality, noise from used to encrypt data while being sufficiently interpretable by network for...

For epileptic seizure detection and prediction, to address the computational bottleneck of von Neumann architecture, we develop an in-memory memristive crossbar-based accelerator simulator. The simulator software is composed a Python-based neural network training component MATLAB-based crossbar array component. provides baseline for developing deep learning-based signal processing tasks, as well platform investigate impact weight mapping schemes device peripheral circuitry non-idealities.

Memristors have the potential to significantly impact memory market, and demonstrated for analog computing within a sub-class of neuro-inspired information processing. In order enable circuit designers use test memristor/CMOS hybrid circuits, it is necessary an accurate reliable memristor model. this work, new model based on Charge Transport Mechanism (CTM) presented. This paper analyzes different current mechanisms that exist in Schottky barrier region memristors: direct tunneling,...

Memristor is considered as a suitable alternative solution to resolve the scaling limitation of CMOS technology. In this paper, fast, low area and power hybrid CMOS-memristor based Linear Feedback Shift Register (LFSR) design proposed. As an example 4-bit LFSR has been implemented by using Ratioed Logic (MRL) scheme with 64 devices memristors. The proposed more efficient in terms when compared CMOS-based circuits. simulation results proves functionality design. This approach presents...

Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, switch technology is immature suffers from numerous imperfections, which are often considered limitations implementations artificial Nevertheless, a reasonable amount variability can harnessed implement efficient probabilistic approximate computing. This...

Responsive deep brain stimulation (DBS) requires recruiting structures without affecting the superficial neuronal population. Neurosurgeons widely use implanted electrodes, which are highly localized but invasive, to stimulate brain. Temporally interfering (TIS) excites non-invasively. This neuromodulation technique utilizes two high-frequency sinusoidal electric fields that do not recruit neural have a small frequency differential. The differential causes low-frequency interference envelope...

Abstract Auto-encoders are capable of performing input reconstruction, denoising, and classification through an encoder-decoder structure. Spiking Auto-Encoders (SAEs) can utilize asynchronous sparse spikes to improve power efficiency processing latency on neuromorphic hardware. In our work, we propose efficient SAE trained using only Spike-Timing-Dependant Plasticity (STDP) learning. Our auto-encoder uses the Time-To-First-Spike (TTFS) encoding scheme needs update all synaptic weights once...

Computers transform to the smaller, faster and more reliable devices year by year. Accordingly designing efficient logic gates, as basic blocks of VLSI chips, are essential for circuit designers. Since integration reached its limits through conventional technologies mainly CMOS based designs quest novel promising was commenced. Memristor is a passive element that has been fabricated recently taken increasing attentions. Less area non-volatility most important properties this element. Also...

These days, there is an increasing interest in implementation of spiking neural systems that can be used to perform complex computations or solve pattern recognition tasks like mammalian neocortex. In this paper, Morris-Lecar neuron utilized implement bio-inspired memristive network for unsupervised learning applications. The spike timing dependent plasticity mechanism has been applied as the scheme system. analyzed. Also memristors are synapses proposed system reproduce long term...