The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets data. More recent computing paradigms, such as high parallelization near‐memory computing, help alleviate data bottleneck to some extent, but paradigm‐shifting concepts are required. In‐memory has emerged a prime candidate eliminate this by colocating processing. In context, resistive switching...

Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due their ability natively perform in-memory fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need be compatible with fabrication processes...

In recent years, resistive memories have emerged as a pivotal advancement in the realm of electronics, offering numerous advantages terms energy efficiency, scalability, and non-volatility [1]. Characterized by their unique switching behavior, these are well-suited for variety applications, ranging from high-density data storage to neuromorphic computing [2]. Their potential is further enhanced compatibility with advanced semiconductor processes, enabling seamless integration into modern...

Exploration of memristors' behavior at cryogenic temperatures has become crucial due to the growing interest in quantum computing and electronics. In this context, our study focuses on characterization (4.2 K) TiO2−x-based memristors fabricated with a CMOS-compatible etch-back process. We demonstrate so-called reforming (CR) technique performed 4.2 K overcome well-known metal-insulator transition (MIT), which limits analog low temperatures. This process was found be reproducible led durable...

The development of metallic single-electron transistor (SET) depends on the downscaling and electrical properties its tunnel junctions (TJs). These TJs should insure high-ON current, low-OFF low capacitance. We propose an engineered TJ based multidielectric stacking. A number high-k low-k materials were considered to optimize TJ's characteristics. optimized is proven increase ION current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>...

Current quantum systems based on spin qubits are controlled by classical electronics located outside the cryostat. This approach creates a major wiring bottleneck, which is one of main roadblocks toward scalable computers. Thus, we propose memristor-based programmable dc source that can perform biasing dots (QDs) inside novel cryogenic would enable to control applied voltage electrostatic gates programming resistance memristors, thus storing in latter appropriate conditions form QDs. In this...

We have proposed and validated a true hybrid SET/CMOS device, called SETMOS, that is able to extend the Coulomb blockade oscillations of SET transistor into /spl mu/A current range, corresponding near sub-threshold operation region nanometer-scale MOSFET. New nano-scale analog applications, working at sub-ambient temperatures (-150/spl deg/C up 100/spl deg/C), including novel NDR circuit, amplifiers, even NEMS-SETMOS circuit cells are uniquely supported by SETMOS.

The development of metallic single electron transistor (SET) depends on the downscaling and electrical properties its tunnel junctions. These junctions should insure high current levels, low thermionic current, capacitance. authors use atomic layer deposition to fabricate Al2O3 HfO2 thin layers. Tunnel barrier engineering allows achievement capacitance using optimized annealing plasma exposure conditions. Different stacks were designed fabricated increase transparency junction while...

This paper presents a damascene process for the fabrication of titanium micro/nanostructures and nanowires with adjustable thickness down to 2 nm. Their depth is precisely controlled by chemical-mechanical planarization together in-process electrical characterization. The latter, in combination model resistivity versus thickness, allows control metal line nanometer range. In summary, we have developed end point detection method nanostructures. addition, adopted covers geometrical influences...

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential such sources. We first demonstrate operation commercial discrete operational amplifier down to 1.2K which is used on source prototype. Then, tunability validated by performing several 250mV-DC sweeps with resolution 10mV at room temperature 1.2K. Additionally, prototype exhibits limited output drift...

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential such sources. We first demonstrate operation commercial discrete operational amplifier down to which is used on source prototype. Then, tunability validated by performing several -DC sweeps with resolution at room temperature . Additionally, prototype exhibits limited output drift This showcases biasing....

An adaptive inference method for crossbar (AIDX) is presented based on an optimization scheme adjusting the duration and amplitude of input voltage pulses. AIDX minimizes long-term effects memristance drift artificial neural network accuracy. The sub-threshold behavior memristor has been modeled verified by comparing with fabricated device data. proposed evaluated testing different structures applications, e.g., image reconstruction classification tasks. results showed average 60%...

This paper presents the fabrication, together with morphological and electrical characterizations of complementary resistive switches using nanodamascene process. The as-fabricated devices are fully embedded in an insulating oxide, opening way for further process steps such as three-dimensional monolithic integration. Complementary performance is consistent random access memories fabricated characterized same procedure that showed R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

III-V solar cell cost reduction and direct III-V/Si integration can both be realized by depositing a thin layer of high-quality Ge on relatively low-cost Si substrates. However, epitaxial growth substrates is difficult due to the 4% lattice mismatch between film substrate. Threading dislocations (TDs) introduced within have detrimental effect device performances. The goal this research address perennial need minimize defect density epilayers grown We seek accommodate effects introducing...

With this work we have assessed the minimum thickness and grain size realizable for a polysilicon (poly-Si) layer deposited with low-pressure chemical vapour deposition technique. Three different approaches using pure silane in standard horizontal reactor been evaluated: (i) direct poly-Si deposition, (ii) hemispherical silicon (iii) an amorphous (a-Si) followed by crystallization thermal annealing. It has demonstrated that a-Si/crystallization process seems to be best candidate of...

Non-volatile resistive switching devices are considered as prime candidates for next-generation memory applications operating at room temperature and above, such random-access memories or brain-inspired in-memory computing. However, their operability in cryogenic conditions remains to be mastered adopt these building blocks enabling large-scale quantum technologies via quantum-classical electronics co-integration. This study demonstrates multilevel 1.5 K of Al2O3/TiO2-x fabricated with...

This paper presents a comparative study of one-bit-full-adder cell based on metallic complementary capacitively coupled single-electron transistors with its 22 nm CMOS counterpart. Performance and energy efficiency are investigated. The CMOS-like transistor full adder is used in two operating mode, hysteresis non-hysteresis. Parallel serial single electron designs introduced. inverter consumes less than 90.4 pW while it dissipates 4.21 nW technology.

A novel analytical and compact model of Single Electron Transistor (SET) is developed implemented in Verilog-A language for use hybrid SET-CMOS logic circuit design. The based on the steady state Master-Equation (ME). implementation this original simple model, taking into account physical characteristics tunnel junctions thermionic emission, has faithfully reproduced behavior metallic SET operating at room temperature. universal gate cell analyzed to illustrate efficiency model.

This paper reports ultrahigh-sensitive and ultralow-power CMOS compatible pH sensors that are developed in the back-end-of-line (BEOL) of industrial 28-nm ultrathin body buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) transistors. Fabricating sensing gate control a capacitive divider circuit, demonstrated where front bias is applied through rather than bulky reference electrode. On other hand, strong electrostatic coupling between back FDSOI devices provide an intrinsic...

A new logic family based on ultra-thin film (10nm) nanograins (5 to 20nm) polysilicon wires (polySiNW) is proposed, validated and studied. This can be operated from 4K up 400K hybridized with conventional CMOS. Ultra low power dissipation in the order of hundreds pWs has been observed, which outperforming CMOS technology, terms consumption, by orders magnitude