A5088219910- Copper Interconnects and Reliability
- Semiconductor materials and devices
- Graphene research and applications
- Electronic Packaging and Soldering Technologies
- Advancements in Battery Materials
- 3D IC and TSV technologies
- Electrodeposition and Electroless Coatings
- Semiconductor materials and interfaces
- Metal and Thin Film Mechanics
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon and Solar Cell Technologies
- Advancements in Photolithography Techniques
- GaN-based semiconductor devices and materials
- Aluminum Alloys Composites Properties
- Advanced Surface Polishing Techniques
- Carbon Nanotubes in Composites
- Plasma Diagnostics and Applications
- Metallurgy and Material Forming
- Electron and X-Ray Spectroscopy Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Fiber-reinforced polymer composites
- Silicon Carbide Semiconductor Technologies
- Molecular Junctions and Nanostructures
- Supercapacitor Materials and Fabrication
- ZnO doping and properties
Shibaura Institute of Technology
2014-2024
Sumitomo Heavy Industries (Japan)
2016
Toray Industries, Inc. (Japan)
2012
NEC (Japan)
1990-2006
Renesas Electronics (United States)
2006
Tokyo Electron (Japan)
2002
Jikei University School of Medicine
1999
Kagoshima University
1987-1995
Abstract Using a novel hybrid conductor with intercalated multilayer graphene (I-MLG) and Ni, it was demonstrated that the area of radio frequency (RF) patch antenna at around 18 GHz can be reduced by one-third. Improved intercalation doping MLG realized split-CVD method for improved crystallinity uniformity higher to MLG. With process improvement, sheet resistance I-MLG layer current considered flow preferentially in skin effect high frequencies, kinetic inductance induced layer. In...
Room-temperature recrystallization (self-annealing) of electroplated copper (Cu) films is investigated using three kinds seed/barrier layers with nontexture and (111) texture. The as-plated have almost the same texture as seeds. changes during self-annealing depend on seed increases for film deposited layer, but decreases layers. For all plated films, tensile stress after self-annealing, which corresponds to shrinkage. Recrystallization rate Cu layer higher than one seed. It postulated that...
Electroless NiWP and NiReP films were investigated with the aim of application to barrier capping layers in interconnect technology. These alloys containing a refractory metal high melting point expected have ability avoid diffusion Cu into interlevel dielectric. The composition resistivity these first order know relation between its thermal stability. stability was by measuring sheet resistance cross-sectional observation field emission scanning electron microscope. Additionally, an...
A new fabrication process for an electrolessly deposited NiReP barrier layer on is proposed ultralarge scale integration applications. The film was formed without sputtered seeds by utilizing a self-assembled monolayer (SAM) as adhesion and catalyst layer. For the electroless deposition covered with SAM, acid or neutral bath suitable whereas alkaline solution damaged surface. To fabricate consistently uniform surface, two-step process, consisting of nucleation step performed in formation...
The moisture barrier properties of stacked graphene layers on Cu surfaces were investigated with the goal improving efficiency single-layer (SLG) for metallization. SLG large grain size coated CVD-SLG to cover grain-boundaries and defective areas underneath film, which was confirmed be oxidized by Raman spectroscopy measurements. To evaluate humidity resistance graphene-coated surfaces, temperature storage (THS) testing conducted under accelerated oxidation conditions (85 °C 85% relative...
We investigated the electroless CoWP/NiB diffusion barrier layer for ultralarge-scale integration (ULSI) interconnection by forming immobilizing Pd catalyst on an organosilane layer. When CoWP film was formed directly a Pd-activated layer, it became islandlike and did not form continuous NiB deposited uniform 10 nm thick. The transmission electron microscopy images of interfaces showed that, at annealing temperature up to 30 min, remained unchanged clear, showing no trace Cu into substrate....
We investigated doping material selection for multilayer graphene (MLG) interconnects and a passivation process to stabilize the doped state. Intercalation with Br2, FeCl3, MoCl5 was compared in terms of ability robustness against environmental effects, which are exacerbated by miniaturization. found that advantageous hypothesized stability would be enhanced partially oxidizing avoiding hydrolysis water vapor air. To test this, we examined dry oxygen exposure. verified effect improved...
After etching in a /Ar electron cyclotron resonance plasma, /SiN/Cu via structures for multilevel Cu interconnection were investigated with angle‐resolved x‐ray photoelectron spectroscopy. Photoelectron shadowing, determined by spectroscopy takeoff angle, and electrostatic charging used to determine the chemical composition amount of contamination on dielectric horizontal surfaces sidewalls, as well at bottoms holes. All covered one two monolayers layer . The also small (∼0.1 monolayers) Cu,...
Multilayer graphene (MLG) is expected to be a low-resistance and high-reliability interconnect material replacing copper (Cu) in nanoscale interconnects. To achieve with MLG, carrier doping necessary since the concentrations pristine MLGs are low. In this work, effects of bromine (Br) by intercalation on concentration sheet resistance exfoliated highly oriented pyrolytic graphite (HOPG) were investigated measuring Fermi level shift using ultraviolet photoelectron spectroscopy (UPS)...
Abstract To improve the crystallinity of multilayer graphene (MLG) by CVD at a low temperature, effect current stress during thermal on cobalt (Co) catalytic layer was investigated. The MLG obtained with higher than that without same temperature. This indicates has effects besides Joule heating effect. Co and growth reaction were investigated, it found had small grain size crystal structure catalyst large such as activation energy 0.49 eV, which is close to value reported for carbon surface...
As promising technologies for fabrication of highly reliable Cu interconnects, using Ti barrier metal (Cu/Ti) and chemical vapor deposition (CVD) Co capping (Co/Cu/Ta/TaN) were compared. Both interconnects similarly showed longer electromigration (EM) lifetime larger activation energy than conventional fabricated Ta/TaN without (Cu/Ta/TaN). The residual resistance lines was measured cryogenically. Cu/Ti a higher Co/Cu/Ta/TaN Cu/Ta/TaN, which indicates the presence more impurities density...
In order to address the process requirements of leading-edge image sensors, a new single-wafer ultra-high energy ion implanter, S-UHE, has been developed. This product incorporates two exceptional subassemblies. One is eighteen-stage RF linear accelerator from UHE, multi-wafer offering maximum beam 2MeV per charge. The other field proven end station used by MC3-II/GP, medium current which can provide throughput over 450 wafers/hour. S-UHE unique line concept where analyzing magnets bend...
Cleaning processes for CHF3 reactive ion etched Cu vias, consisting of exposure to a hydrogen plasma, an oxygen and hexafluoroacetylacetone [H(hfac)] vapors have been investigated. After each step in the cleaning process, dielectric surface via structures were analyzed by situ angle-resolved x-ray photoelectron spectroscopy. A plasma was effective removing carbon fluorine deposits on all surfaces, CuO Cu2O at bottom. It not effective, however, deposited surfaces. An is some deposits....
A high g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> , 375 mS/mm (V xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> = -0.09 V), has been achieved from a 0.3 µm long gate GaAs MESFET with very small short channel effect by employing an MBE grown layer. The maximum K - value obtained was 410 mS/Vmm, which is the highest ever reported for MESFETs. unique technology, combining sidewall assisted self alignment technology (SWAT) and...
In order to develop highly reliable Cu interconnects, temperature dependence of the electromigration (EM) lifetime metal (CoWP) capped interconnects is investigated. It found that EM enhanced as test rise from 275 380 °C. NH3 plasma treatment before dielectric cap layer deposition on CoWP influenced lifetime, is, without have longer than those with at higher temperatures. investigate mechanism for this enhancement, micro-analysis and failure mode analysis were carried out. concluded Co...
Stress-induced voiding (SIV) was investigated for 130 nm node dual-damascene Cu interconnects. Three SIV failure modes were revealed by TEM analyses. Cumulative at various metal widths, via shape and position on a line 150/spl deg/C which the maximum rate observed. narrow also observed, is associated with tensile stress in calculated 3D finite element method (FEM) analysis. Stress relaxation dielectric structure quenching process demonstrated based simulation, thus resulting suppressed.
A variation in the reactive ion etch (RIE) rate of silicon oxynitride ( SiOxNy) films deposited by plasma-enhanced chemical vapor deposition was studied CHF3 RIE, CHF3+carbon mono-oxide (CO) RIE and CF4 RIE. The source gas flow ratio (R=N2O/SiH4) during SiOxNyfilm varied to obtain a film different atomic composition. Etch rates decreased order CHF3+CO selectivity SiO2 over SiOxNy increased same also. fluorocarbon CFx) process analyzed x-ray photoelectron spectroscopy measurements. are found...
A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. stable intermetal dielectric (IMD) integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and single damascene (S/D) Cu-plug structure applied. An 18% reduction in capacitance obtained compared that SiO2 IMDs. The superior controllability thickness S/D process enables us to enhance MPU maximum frequency easily....
As the wiring-space decreases, time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction TDDB lifetime will be required. In this investigation, dependences on temperature electric field are studied comprehensively for 90- 65-nm-node Cu/SiOC using practical multilevel test structures with via plugs. Low-electric-field tests down to 1 MV/cm were carried out by package method high up 300 °C....