In this work, third-quadrant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – notation="LaTeX">$V$ characterization and surge current tests are carried out on SiC asymmetric-trench MOSFET (DUT A) double-trench B) under various gate–source biases ( notation="LaTeX">$V_{\mathrm {GS}}$ ). The capability is found to be uninfluenced by for DUT A. However, it has a 71.4% increase...

This paper demonstrates a SiC lateral MOSFET (LMOS) with DOUBLE RESURFs (reduce surface field) technology to improve the device's breakdown voltage. The electrical characteristics and analysis of fabricated LMOS are carried out in terms output, transfer blocking characteristics, as well leakage current mechanisms. In particular, effect length P-top on device performance is studied. experimental results indicate that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this work, the influence of JFET region width on device's performance and avalanche reliability is studied 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated a 4-in SiC wafer. Unclamped inductive switching (UIS) test conducted to compare devices under tests (DUTs) capability at both <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 -5 V. At V, best achieved with 4 μm. Through mix-mode TCAD simulation, channel conduction...

This paper demonstrated the impact of process conditions on surge current capability 1.2 kV SiC junction barrier Schottky diode (JBS) and merged PiN (MPS). The influence ohmic contact defect density produced by implantation was studied in simulation. device fabricated with high temperature had less implant region compared room implantation, which contributed to higher hole injection mode 20% improvement. In addition, lower P+ resistance, capability. When fabrication a single metal layer...

In this article, a structure design concept plasma spreading layer (PSL) has been introduced into planar silicon carbide (SiC) MOSFETs. Devices’ static characteristics, gate–drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}{)}$ </tex-math></inline-formula> , and short-circuit (SC) robustness are studied with experiments. The PSL can increase the breakdown voltage (BV)...

In this work, the avalanche capability of 1. 2kV 4H-SiC JBS and MPS diodes in single-pulse Unclamped Inductive Switching (UIS) tests is investigated compared. It found that width (W) wide P+ region has great effects on device capability. The experimental results show gets increased with W when W=3-8μm, then declines exceeds 8μm. TCAD Simulation carried out to study behavior mode. revealed electric field under condition crowded at corners pn junction, which leads current crowding unbalanced...

In this work, repetitive surge current stress is applied on the body diode of SiC MOSFET to examine degradation diode. The tests are conducted at $25^{\circ}\mathrm{C}$ and $125^{\circ}\mathrm{C}$. Static characteristics reverse recovery transient DUT's measured after each 50 pulses monitor electrical parameter variations. Increase in resistance decrease charge observed hundreds cycles. Meanwhile, transfer curve I-V DUT measured. No obvious shift threshold voltage observed, indicating no...

In this work, the influence of JFET region width on 1200V SiC MOSFET's avalanche reliability is studied with unclamped inductive switching (UIS) test. It revealed that highest capability achieved a 4μm. As presented in TCAD silmulation, locallized heat accumulation arising from high channel current density proves to be failure mechanism. Furthermore, balance between device performance and different design discussed by considering device's figure merits (FOM).

Although the body diode of SiC MOSFET has excellent surge capability, reliability issues about commercial under repetitive current stress haven't been studied thoroughly. In this work, is applied to trench MOSFET, and tests are conducted different gate biases ambient temperatures. It found that no bipolar degradation occurs in but phenomena oxide package observed devices (DUTs). At room temperature, threshold voltage (VT8) related degrades more seriously at a negative bias -5V than 0V. 0V...

In this article, SiC Merged PiN Schottky (MPS) diodes with hexagonal and circular cell designs are investigated compared in terms of characteristics ruggedness. It is demonstrated by experimental simulated methods that the design brings better performance than one. Owing to almost simultaneously triggering P+ island ring under high current stress, distribution more balanced, which significantly reduces forward voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A method of fabricating submicron gratings for optoelectronic devices from a glass mask was proposed and demonstrated. The has on both sides with period at least four times the final feature size. By modifying grating periods mask, one can achieve multiple-period very fine spacing advanced wavelength division multiplexing (WDM) devices. In this letter, we demonstrated 0.5 μm second-order 1.55 distributed-feedback lasers 6 Å difference WDM laser arrays using only optical sources.

In this paper, the single pulse avalanche robustness of 1.2kV 4H-SiC Junction Barrier Schottky (JBS) diode with different designs is investigated. The unclamped inductive switching (UIS) tests are carried out to obtain energy capability. It found that JBS narrower spacing P+ region exhibits higher (around 5%~8.5% improvement in paper). Simulation analysis reveals there a current crowding mode, which will be more severe increasing regions. localized and unbalanced distribution can lead...

In this paper, a new structure named plasma spreading layer (PSL) is introduced into planar SiC MOSFETs to improve the short-circuit robustness. The performance under 400V, 600V, and 800V bus voltage tested. And two failure modes are discovered. 3D TCAD simulations, Emission Microscope (EMMI), Focused ion beam (FIB) used investigate mechanisms. Under 400V 600V voltage, interlayer dielectric between source gate damaged due high temperature generated in process, melted metal Al connected...

A good tooth cusp extraction is helpful in evaluating the effect of cosmetic dental work virtual surgery. We propose a new extraction, which integrates DBSCAN (density-based spatial clustering applications with noise) algorithm neighborhood search to extract from three-dimensional cloud-point model. This method used point cloud height and curvature screen out dented set. Then we employ segment different feature regions surface generate candidate Finally, set was accurately located at apex...

In this work, the influences of P-well design and turn-off gate-to-source bias on surge robustness SiC MOSFET’s body diode are studied. Devices with high low doping concentration designs stressed current pulses when is biased 0 or −5 V. The found to have effects capability doping-designed device. case 0-V bias, channel prone turning acquires a higher than devices under On other hand, device less influenced by bias. Furthermore, threshold voltage instability after repetitive also...

Optically aided reading and writing of gold tungsten mounds on proton-implanted, multiple quantum well InGaAs/GaAs wafers has been demonstrated using an atomic force microscope (AFM). The system is relatively simple, requiring only a diode laser as the light source, providing novel, compact, optoelectronic memory system.

The 1.2 kV split-gate and split-source MOSFET with integrated JBS diode is fabricated. two types of devices different Schottky widths (1 µm 2 µm) are designed static characteristics compared. Additionally, the short circuit capability failure mechanism analyzed. leakage current at high temperature leads to destruction devices.

4H-SiC Trench-gate MOSFET with JTE terminationIn this paper, a trench-gate is reported detailed introduction on cell design, fabrication and characterization. The proposed features an asymmetric structure, in which the channels are distributed along a-face (11-20). High energy Al ion implantation utilized to form deep P+ shielding region, alleviates electric field crowding oxide layer at bottom of gate trench. In terms termination, structure designed realized single-step ICP etching....

SiC MOSFET Body diodes are expected to compete against schottky barrier (SBD) in high power applications. To investigate the surge capability of body commercial MOSFETs, single pulse and repetitive current tests processed on DUTs. In test, DUTs stressed failure. Compared with trench-gate planar-gate MOSFETs tend show better at all rated levels. On other hand, degradation electrical parameters is observed after hundreds cycles. The mechanism bipolar oxide layer has been analyzed.

Ultra-high capacity information storage is a goal pursued by many researchers in the fields of optical computation and signal processing. We present for first time new technique combining electro-optic probing micromechanical tips to perform readout writing an ultra-high memory. Potentially, this could achieve density 1 Terabit/cm/sup 2/.

In this work, the avalanche ruggedness of 1200V /2A SiC MPS diodes with hexagonal and circular cells are studied through experiment, modeling analysis, 3D- TCAD simulation. The experimental result demonstrated that energy/current capability cell-designed diode (MPS-B) exhibit higher than one (MPS-A). Further analysis simulation results both reveal MPS-A cell design will suffer junction temperature rise (ΔT <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...