A5070809707- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Advanced Neural Network Applications
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Tensor decomposition and applications
- Neural Networks and Applications
- Computational Physics and Python Applications
- CCD and CMOS Imaging Sensors
- Quantum Mechanics and Applications
- Ferroelectric and Negative Capacitance Devices
- Quantum Information and Cryptography
- Cloud Computing and Resource Management
- Domain Adaptation and Few-Shot Learning
- VLSI and Analog Circuit Testing
- VLSI and FPGA Design Techniques
- Advanced Image and Video Retrieval Techniques
- Cold Atom Physics and Bose-Einstein Condensates
- Distributed and Parallel Computing Systems
University of Illinois Urbana-Champaign
2021-2023
Kyung Hee University
2013
Yonsei University
2013
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient space exploration (DSE). Existing HLS tools are built using compiler infrastructures largely based on a single-level abstraction, such LLVM. How-ever, designs typically come with intrinsic structural or functional hierarchies, different optimization problems often better solved levels of abstractions. This paper proposes ScaleHLS <sup>1</sup>, new scalable...
This paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile C/C++ programs and PyTorch models to highly-efficient synthesizable C++ designs. The original ScaleHLS achieved significant speedup on both kernels [14]. In this paper, we first highlight the key features tackling challenges present in representation, optimization, exploration large-scale To further improve scalability then propose transform analysis library supported...
The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms such as FPGAs. However, high-quality FPGA design is very hard to create it requires expertise long iteration time. In contrast, software typically developed in short development cycle, high-level languages like Python, which at much higher level abstraction than all existing flows. To close this gap simplify programming, we...
High-Level Synthesis (HLS) has enabled users to rapidly develop designs targeted for FPGAs from the behavioral description of design. However, synthesize an optimal design capable taking better advantage target FPGA, a considerable amount effort is needed transform initial into form that can capture desired level parallelism. Thus, space exploration (DSE) engine optimizing large complex achieve this goal. We present new DSE considering code transformation, compiler directives (pragmas), and...
The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms such as FPGAs. However, high-quality FPGA design is very hard to create it requires expertise long iteration time. In contrast, software typically developed in short development cycle, high-level languages like Python, which at much higher level abstraction than all existing flows. To close this gap between flows applications,...
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient space exploration (DSE). Existing HLS tools are built using compiler infrastructures largely based on a single-level abstraction, such LLVM. However, designs typically come with intrinsic structural or functional hierarchies, different optimization problems often better solved levels of abstractions. This paper proposes ScaleHLS, new scalable customizable...
Compression technologies for deep neural networks (DNNs), such as weight quantization, have been widely investigated to reduce the model size so that they can be implemented on hardware with strict resource restrictions. However, one major downside of compression is accuracy degradation. To deal this problem effectively, we propose a new compressed network inference scheme high but slower DNN coupled its highly version typically delivers much faster speed lower accuracy. During inference,...
Machine learning is one of the most popular fields in current era. It used various areas, such as speech recognition, face medical diagnosis, etc. However, problem that neural networks for machine applications are becoming too large and slow they get more complicated powerful. This gets especially serious when edge devices with a small chip. As result, researchers have proposed two major solutions to solve this problem.