Matthew Breeding

ORCID: 0000-0001-9637-5840
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About
Contact & Profiles
Research Areas
  • Radiation Effects in Electronics
  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis
  • Low-power high-performance VLSI design
  • Advanced Memory and Neural Computing
  • Advanced Data Storage Technologies
  • Advanced Semiconductor Detectors and Materials
  • Radiation Detection and Scintillator Technologies
  • VLSI and Analog Circuit Testing
  • Advancements in Semiconductor Devices and Circuit Design
  • Software-Defined Networks and 5G

Sandia National Laboratories
2021-2025

Vanderbilt University
2019-2021

Single-event upsets are observed in a 72-layer 3-D NAND flash memory operated single-level cell mode after low-energy proton (500 keV-1.2 MeV) and heavy-ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of protons within stack, Monte Carlo simulations correlated with experimental data. Direct ionization by identified data analysis energy dependence device-sensitive cross section. Heavy-ion also presented for comparison.

10.1109/tns.2021.3063156 article EN IEEE Transactions on Nuclear Science 2021-03-05

This work shows that the static random access memory (SRAM) error rate for a commercial 65-nm device in dose environment can be highly dependent upon integrated (dose <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> pulse duration). While typical metric such testing is upset (DRU) level rad(Si)/s, series of experiments at Little Mountain Test Facility (LMTF) dependence...

10.1109/tns.2023.3283310 article EN IEEE Transactions on Nuclear Science 2023-06-14

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level at a system scope, we present multiscale simulation framework. Charge collection the 1) device level determines 2)...

10.1109/tns.2021.3071653 article EN IEEE Transactions on Nuclear Science 2021-05-01

The complex vertical structures of 2.5D/3D integrated circuits present new challenges for the simulation, experimentation, and analysis soft errors. Each added layer circuitry in vertically technologies increases requirement interconnect metallization. proximity these metal layers to sensitive regions may result materials-dependent responses radiation. Monte-Carlo simulations offer flexibility utility exploring impact geometry material selection on resulting radiation response...

10.1109/irps.2019.8720545 article EN 2022 IEEE International Reliability Physics Symposium (IRPS) 2019-03-01
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