A5017620177- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Particle Detector Development and Performance
- Horticultural and Viticultural Research
- Radiation Detection and Scintillator Technologies
- Nuclear and radioactivity studies
- VLSI and FPGA Design Techniques
- Advanced Memory and Neural Computing
- Interconnection Networks and Systems
- Garlic and Onion Studies
- Photonic and Optical Devices
- Network Time Synchronization Technologies
- Embedded Systems Design Techniques
- Particle accelerators and beam dynamics
- Neutrino Physics Research
- Electrostatic Discharge in Electronics
- Ion-surface interactions and analysis
- Internet of Things and Social Network Interactions
- Risk and Safety Analysis
- Optical Imaging and Spectroscopy Techniques
- Wireless Body Area Networks
- Metallurgy and Material Science
Oak Ridge National Laboratory
2023
Sandia National Laboratories California
2021-2022
Sandia National Laboratories
2018-2022
Arizona State University
2022
Brigham Young University
2014-2020
Indiana University Bloomington
2008
Institute of Chemistry
1907
University of Richmond
1906
Society of Chemical Industry
1905
Royal Society
1905
This study examines the single-event response of Xilinx 28 nm Kintex-7 FPGA irradiated with heavy ions. Results for effects on configuration SRAM cells, user-accessible Flip-Flop and BlockRAM™ memory are provided. also describes an unconventional single event latch-up signature observed during testing.
Low- and high-energy proton experimental data error rate predictions are presented for many bulk Si SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute total on-orbit single-event upset (SEU) rate. Every effort was made predict LEP rates that conservatively high; even secondary generated in spacecraft shielding have been included analysis. Across all environments investigated, when operating within 10% of nominal voltage, LEPs were...
This study examines the single-event response of Xilinx 20 nm Kintex UltraScale Field-Programmable Gate Array irradiated with heavy ions. Results for latch-up and upset on configuration SRAM cells Block RAM memories are provided.
Triple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within configuration memory static random access field-programmable gate arrays. Applying TMR design successfully reduces design's neutron cross section by 80×. The effectiveness TMR, however, is limited presence single bits in which cause more than one domain fail simultaneously. We present three strategies mitigate against these failures and improve TMR:...
TMR combined with configuration scrubbing is an effective technique to mitigate against radiation-induced CRAM upsets on SRAM-based FPGAs. However, its effectiveness limited by low-level common mode failures due the physical mapping of a design FPGA device. This paper describes how are introduced during implementation process and introduces approach for resolving them through custom incremental placement tool Xilinx 7-Series Multiple designs across multiple generations devices shown be...
This study examines the single-event response of Xilinx 16nm FinFET UltraScale+ FPGA and MPSoC device families. Heavy-ion latch-up, upsets in configuration SRAM, BlockRAM™ memories, flip-flops, neutron-induced latch-up results are provided.
We have built a detector capable of locating high Z objects in the sampling (middle) region detector. As atomic number increases, radiation length rapidly decreases, yielding larger variance scattering angle. Cosmic ray muon tomography works by tracking muons above region, and them below as well. The difference between two trajectories yield information, via variance, materials contained within region[1]. One most important aspects cosmic is minimizing exposure time. flux about 1/cm\^2/min,...
Triple modular redundancy (TMR) with repair is a commonly employed mitigation strategy used on SRAM field-programmable gate arrays (FPGAs) to reduce the effects of ionizing radiation and improve circuit's sensitive cross section. This article examines TMR circuits, where I/O ports circuit have not been triplicated, but internal circuitry has. Such circuits introduce single-point failures (SPFs) into that limit neutron cross-sectional improvement offered by only 3× for b13 benchmark in this...
This paper presents an examination of the Xilinx 7-Series GTX transceiver for use in High Energy Physics (HEP) experiments with special emphasis on environment expected ATLAS Liquid Argon (LAr) subsystem. Two Kintex 325T devices were tested a 180 MeV proton beam at TSL facility Sweden. The test architecture monitors transceivers lane failures and bit errors data streams from 13 links sent Device Under Test (DUT). DUT was exposed to 1.55 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology.A test structure is presented that approximately measures the length SETs using flip-flop shift registers with clock inputs driven by an inverter chain.The was irradiated ions at linear energy transfers (LETs) 4.0, 5.6, 10.4, and 17.9 MeV-cm 2 /mg, cross sections SET pulses measured down to 12.7 ps are presented.The experimental results interpreted modeling methodology...
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Edge devices are being deployed at increasing volumes to sense and act on information from the physical world. The discrete Fourier transform (DFT) is often necessary make this sensed data suitable for further processing $\unicode{x2013}$ such as by artificial intelligence (AI) algorithms transmission over communication networks. Analog in-memory computing has been shown be a fast energy-efficient solution edge AI workloads, but not transforms. This because of existence (FFT) algorithm,...
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Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level at a system scope, we present multiscale simulation framework. Charge collection the 1) device level determines 2)...
Small spot size laser testing for single-event effects has proven to be a particularly productive path insights on the physics of charge collection and circuit response that are difficult or impossible obtain through broad ion beam tests. As result, there number such facilities; example, four them were compared in 2012 [1], but relatively new facility at University Saskatchewan offers unique galvo-mirror, laser-spot scanning capability addition usual micrometer-based DUT motion stage [2]....
We describe the porting of a soft-error (SE) hardened microprocessor to modern 12-nm bulk CMOS finFET fabrication process and radiation testing results. The includes latch-based cache main register file (RF) arrays, with compact dual-patterned layouts. It is protected by dual modular redundancy (DMR) in speculative pipeline, RF, caches. Self-correcting triple redundant (TMR) flip-flops provide fine-grain protection TMR circuits that hold key architectural state. DMR are checking at caches,...
Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop slave latches self-correct the clock low phase using Muller C-elements latch feedback. These driven by two stored values and not itself, saving area over similar implementation majority gate as large shift-register arrays on test chip have been experimentally tested their mitigation static dynamic modes of...
Triple modular redundancy (TMR) is commonly employed to increase the reliability and mean time failure (MTTF) of a system. This improvement can be shown by using continuous Markov chain. However, typical chain models do not model common cause failures (CCF), which singular event that simultaneously causes in multiple redundant modules. paper introduces new CCF TMR with repair systems. compared idealized without CCF. The fundamental limitations imposes on system are discussed. In motivating...