A5075791862- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Embedded Systems Design Techniques
- Internet of Things and Social Network Interactions
- Radiation Detection and Scintillator Technologies
- Physical Unclonable Functions (PUFs) and Hardware Security
- Radiation Therapy and Dosimetry
Robust Chip (United States)
2016-2017
Vanderbilt University
2008-2016
Universidade Federal do Rio Grande do Sul
2009
Low- and high-energy proton experimental data error rate predictions are presented for many bulk Si SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute total on-orbit single-event upset (SEU) rate. Every effort was made predict LEP rates that conservatively high; even secondary generated in spacecraft shielding have been included analysis. Across all environments investigated, when operating within 10% of nominal voltage, LEPs were...
In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a function operating frequency between 80 MHz and 1.2 GHz. The flip-flops-an unhardened D flip-flop hardened pseudo-DICE were designed in TSMC 40 nm bulk CMOS technology. rates both increase with frequency. Analyses show that an internal single-event transient based upset mechanism is responsible for dependence rates.
Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that combinational logic soft error rate (SER) per gate decreases with scaling. This decrease for SER scaling, however, is not as high latch SER. As a result, proportion errors at chip level shown to increase. Results alpha-particle average sized about 20% node while it only 10% 40-nm 500 MHz. Moreover, frequency which exceeds Factors influence scaling...
Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of transistors plays an important role in single-event upsets (SEU) and system power consumption. Effect V on can be very different for technologies. SEU responses flip-flops logic circuits 20-nm bulk planar 16-nm FinFET technologies with options are investigated. Results show that the technology, design highest threshold among all shows lowest cross-section alpha...
Radiation particles are incident on an integrated circuit (IC) from all angles. For planar technologies, angular incidence increases the deposited charge in a given volume, resulting higher collected at node and more transistors collecting due to increased sharing. FinFET physical structure of is very different that transistor. As result, for incidences will be what has been published technologies. 3D TCAD simulations heavy-ion experiments were carried out investigate effects flip-flop (FF)...
Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the SER changes insignificantly while increases by ∼2x same range. 3D TCAD circuit-level simulations show in single-event transient (SET) pulse width logic gate delay controlling factors, opposing influences on SER.
Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current saturation with respect to increased reduced explains SEU sensitivity flip-flop designs. Experimental cross sections from isotropic Americium-241, 5.4-MeV show irradiation increases by 30 × on average, up orders magnitude, as result device voltage.
In this work, the efforts of an industry wide consortium to characterize logic soft error rate a multitude combinational and sequential circuits across multiple technologies is reported. The basic intent approach was bring together designs intellectual property various semiconductor companies on single technology platform be tested compared under same experimental conditions. This ensures that measured results are validated, comparable benchmarked against other similar designs. More...
The efficiency of transistor sizing and folding techniques to mitigate SET in CMOS circuits is evaluated using circuit device simulations. According the LET ionizing particle, can be more or less filtered by these methods. Based on results simulations, a novel technique able reduce effect proposed. method combines sizing, resistors. was applied chain inverters SRAM cell.
A novel pulsed-latch design using hysteresis that operates similarly to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along standard D-flip-flop (D-FF) and DICE in a 20 nm CMOS process. Alpha Neutron test results indicate ∼26× ∼3× better hardness respectively for the pulsed-hysteresis-latch compared D-FF. The also benefits from 25% higher speed has low area overhead of ∼8% over typical processor utilizing can benefit ∼5× overall reduction...
With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique used to minimize dynamic power consumption and mitigate errors. This work shows that for certain circuits, reduction both errors simultaneously achievable. accomplished by so effective cross section decreases idle sub-circuits can be disabled save power. The proposed method was evaluated experimentally using 4-bit...
Soft-error rates (SER) of Flip-Flop (FF) designs in a 16-nm bulk FinFET technology are characterized with thermal neutron, high-energy neutron and alpha particle irradiations. Results show that the contribution thermal-neutron-induced SER can be higher or lower than alpha-particle-induced for different FF comparable to high-energy-neutron-induced some designs. The overall significantly previously reported.
In large SoCs, managing the effects of soft-errors in flip-flops is essential, however, selective mitigation necessary to minimize area and power costs. The identification optimal set protect typically requires compute-intensive fault-injection campaigns. We present new techniques which group similar into clusters significantly reduce number fault injections. required injections can be lower than total one industrial design with over 100,000 flip-flops, by simulating only 2,100 injections,...
A hardened flip-flop (FF) design using Schmitt-trigger circuits for improved soft-error (SE) performance is presented. The Schmitt-trigger-based DFF (STDFF) along with conventional in a 16-nm bulk FinFET CMOS process were tested alpha particles, heavy-ions, proton, and neutron. STDFF shows ~162× improvement the SE cross-section, up to ~30× heavy-ion ~5× both proton neutron failure time (FIT) rates compared at nominal supply voltage room temperature. also outperformed cross-section over...
In this paper a methodology to predict single-event transient (SET) pulse characteristics is proposed. Analytical models and technology pre-characterization are used estimate SET pulse-widths for different standard cells. The model uses graph analysis of the cell netlist identify similar circuit structures reduced computational complexity characterization error between proposed simulations 3% 9.3%. Model predictions also compared with results from heavy-ion experiments test chip fabricated...
Transistor sizing is a well-known technique to reduce Single Event Transients in nanometer technologies. In this work, the transistor evaluated at 90 nm 3D device model for SET robustness. Mix-mode simulations TCAD were performed three basic logic gates of ST standard cell library. Results indicate that can be more or less efficient according collected charge. For alpha particles, enhance reliability high width sizes, while high-energy particles increase transient pulse amplitude and...
The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate differential FF designs. With small magnitude of input voltages (and resulting noise margins) needed proper operation, sense-amplifier based (SAFF) are susceptible single-event effects (SEE). Single event upset (SEU) performance SAFF investigated in this paper 16-nm bulk FinFET CMOS technology. SEU cross-sections evaluated over particle LET, temperature, and operating frequency....
28-Nm planar, 20-nm and 16-nm FinFET technology combinational flip-flop circuits are investigated using different LET particles. An analytical model is developed to study the ratio of logic (FF) single-event (SE) cross-section as a function Results indicate that high-LET particles have much stronger impact on compared SE for all three nodes.
The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors circuits simulation. proposed improvement in includes both parasitic-bipolar and charge-sharing effects a given technology. Simulation results indicate excellent agreement between published TCAD data 130, 90, 65, 40 nm technology nodes. A comparison ADC rectangular parallelepiped (RPP) integral (IRPP) models indicates 2.7 × 2.5 lower error estimating when...
Single-event upset (SEU) responses of advanced dual- and triple-well planar technologies show significant differences in SEU cross-section for memory cells. The presence the third well alters charge-collection mechanism as increases probability charge sharing, affecting However, at 16-nm FinFET technology node, heavy-ion experiments insignificant between flip-flop (FF) designs operated nominal supply voltage. When voltage is reduced, dual-well particles with low LET values, but not high...
This conference presents the recipients of Outstanding Conference Paper Award from 2015 IEEE Nuclear and Space Radiation Effects Conference.