A5018579479- Radiation Effects in Electronics
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Spacecraft Design and Technology
- Radiation Detection and Scintillator Technologies
- Graphite, nuclear technology, radiation studies
- Radiation Therapy and Dosimetry
- Technology Assessment and Management
- Advancements in Semiconductor Devices and Circuit Design
- Electrostatic Discharge in Electronics
- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Engineering and Test Systems
- Low-power high-performance VLSI design
- Space Technology and Applications
- Advanced Memory and Neural Computing
- Photocathodes and Microchannel Plates
- Nuclear Physics and Applications
- Physical Unclonable Functions (PUFs) and Hardware Security
- Electron and X-Ray Spectroscopy Techniques
- Ion-surface interactions and analysis
- Risk and Safety Analysis
- Ionosphere and magnetosphere dynamics
- Solar and Space Plasma Dynamics
Science Systems and Applications (United States)
2023
Goddard Space Flight Center
2012-2021
Ball (France)
2013-2014
National Superconducting Cyclotron Laboratory
2014
Michigan State University
2014
Moscow Engineering Physics Institute
2014
Los Alamos National Laboratory
2013
Proton (Malaysia)
2013
Analysis Group (United States)
2009
Vanderbilt University
2005-2009
Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used calibrate Monte Carlo rate prediction model, which evaluate the importance of this upset mechanism typical space environments. For ISS orbit and geosynchronous (worst day) orbit, direct major contributor total error rate, but (solar min) proton flux too significant number events. implications these...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) a 45 nm SOI SRAM. The accelerated testing show the SBU-per-bit cross section is relatively constant with technology scaling but MBU increasing. data importance of acquiring analyzing respect to location multiple-bit upsets since relative cells important in determining which can be corrected error...
Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability radiation events (e.g., nuclear reactions), as opposed to classical single-valued LET parameter. Rate conducted with this simulation framework exhibit excellent agreement average observed SEU rate NASA's MESSENGER mission Mercury, while prediction from traditional IRPP method, which does not include contribution ion-ion...
Experimental data are presented that show low-energy muons able to cause single event upsets in 65 nm, 45 and 40 nm CMOS SRAMs. Energy deposition measurements using a surface barrier detector characterize the kinetic energy spectra produced by M20B muon beam at TRIUMF. A Geant4 application is used simulate estimate incident on memories. Results indicate sensitivity this mechanism will increase for scaled technologies.
Low- and high-energy proton experimental data error rate predictions are presented for many bulk Si SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute total on-orbit single-event upset (SEU) rate. Every effort was made predict LEP rates that conservatively high; even secondary generated in spacecraft shielding have been included analysis. Across all environments investigated, when operating within 10% of nominal voltage, LEPs were...
The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both single (SEU) and MBU responses have been shown vary with angle energy for certain technologies. This work analyzes SEU a 130 nm CMOS SRAM which the single-event response shows strong dependence on proton incidence. Current testing methods do not account orientation beam and, subsequently, error rate prediction...
We present experimental evidence of single-event upsets in 28 and 45 nm CMOS SRAMs produced by single energetic electrons. Upsets are observed within 10% nominal supply voltage for devices built the technology node. Simulation results provide supporting that electrons generated incident X-rays. The errors shown not to be result "weak bits" or photocurrents resulting from collective energy deposition Experimental consistent with bias sensitivity critical charge direct ionization effects...
Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm 45 stacked DICE latches are presented. Novel analysis is shown to be important hardness assurance where Monte Carlo with a realistic track structure, along new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one quickly assess the improvements, or limitations, of particular latch design. It was found an effective technique making SEU...
Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI), triple well, guard rings. Although SOI technology is widely reported be immune SEL, conventional pnpn can occur has been observed in non-dielectrically isolated processes. Triple well technologies shown more robust against SEL than dual under all conditions this study, suggesting that introduction a deep...
Device under test
We report low-energy proton and alpha particle SEE data on a 32 nm SOI CMOS SRAM that demonstrates the criticality of using protons for testing highly-scaled technologies. Low-energy produced significantly higher fraction multi-bit upsets relative to single-bit when compared similar data. This difference highlights importance performing hardness assurance with include energy distribution components below 2 MeV. The system-level single-event performance is based technology under investigation...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present an investigation of the observed variations in total dose tolerance emitter-base spacer and shallow trench isolation oxides a commercial 200 GHz SiGe HBT technology. Proton, gamma, X-ray irradiations at varying rates are found to produce drastically different degradation signatures various oxide interfaces. Extraction analysis radiation-induced excess base current, as well...
The laser energy thresholds for SEU SOI 1-Mbit SRAMs built in Sandia's 0.35-μm technology were measured using carrier generation by two-photon absorption. measurements correlated to heavy-ion threshold LET determine an empirical relationship between and LET. This was used estimate the LETs other circuits IBM's 45 65-nm technologies. For ASIC estimated from close However, a dual-port SRAM also 45- IBM SRAMs, did not correlate LETs. likely cause of discrepancy testing is due pulse...
The astronomical community continues to be interested in suitable programmable slit masks for use multiobject spectrometers (MOSs) on space missions. There have been ground-based MOS utilizing digital micromirror devices (DMDs), and they proven highly accurate reliable instruments. This paper summarizes the results of a continuing study investigate performance DMDs under conditions associated with deployment. includes response accelerated heavy-ion radiation, vibration mechanical shock loads...
Delayed charge collection from ionizing events outside the deep trench can increase SEU cross section in isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer reduce delayed that occur by almost an order magnitude, implying approximately comparable reduction
Device-level current transients are induced by injecting carriers using two-photon absorption from a subbandgap pulsed laser and recorded wideband transmission measurement equipment. These exhibit three distinct temporal trends that depend on pulse energy as well the transverse vertical charge generation location. The nature of transient is controlled both behavior subcollector-substrate junction isolation biasing. However, substrate potential modulation, due to deformation depletion region,...
SiGe HBT heavy ion-induced current transients are measured using Sandia National Laboratories' microbeam and high-and low-energy broadbeam sources at the Grand Accélérateur d'Ions Lourds University of Jyväskylä.The data were captured a custom broadband IC package real-time digital phosphor oscilloscopes with least 16 GHz analog bandwidth.These provide detailed insight into effects ion strike location, range, LET.
We measured low-energy proton radiation induced soft error rates (SER) of standard and reduced-SER (RSER) latches, manufactured in 32 nm 45 bulk CMOS technologies, conclude that sequential logic elements built these technologies are not yet susceptible. Further, our results demonstrate at energies where direct ionization dominates, critical charge (Qcrit) plays a far bigger role than above the nuclear reaction threshold.
The potential for using the degraded beam of high-energy proton radiation sources hardness assurance testing ICs that are sensitive to direct ionization effects explored. SRAMs were irradiated high energy (~67-70 MeV). was plastic or Al degraders. Peaks in SEU cross section due observed. To best observe effects, one needs maximize number protons spectrum below threshold. SRIM simulations show there is a tradeoff between increasing fraction with low energies by decreasing peak and reduction...
A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a bulk CMOS SRAM. Detailed descriptions the sensitive regions based upon technology computer-aided design calibration are conjunction with physics-based Monte Carlo simulator predict cross sections that good agreement experimental results
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The was validated using published heavy ion new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM BiCMOS process. Calibrating sufficient reproduce without further adjustment. is used calculate upset event rates low-earth...
Microbeam measurements and TCAD simulations are used to examine the effects of ion angle incidence on charge collected from events occurring in a Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT). The results identify geometrically driven charge-collection mechanisms that dominate low LET broad beam SEU response. deep trench isolation surrounds transistor significantly modulates transport and, therefore, by collector. A new way estimating critical charge, , for upset SiGe HBT...
Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing technologies. This paper reports accelerated neutron testing on 90-nm SRAM that exhibits an increased multiple-bit upset FIT from neutrons at large angles incidence. The modeling these data is used to predict ground-based systems.
Heavy ion-induced single event latchup (SEL) is characterized in a commercially available CMOS readout integrated circuit operating at cryogenic temperatures. SEL observed 24 K and below believed to be possible when free carriers produced by an ion strike initiate exponential increase the carrier density via shallow-level impact ionization (SLII). This results large current that proceeds sustained latched state, even though classic condition for parasitic bipolar gain product not met since...
Laser and heavy-ion data reveal the areas shapes of single-event latchup (SEL)-sensitive regions in CMOS test structures their positions relative to affected p-n-p-n paths. Contrary previous two-dimensional studies, this three-dimensional study shows that position maximum SEL sensitivity these is not centered on a region, but between two neighboring regions, suggesting synergistic triggering increases sensitivity. The SEL-sensitivity maps suggest laser light scattered from metal lines toward...