A5100747869- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Copper Interconnects and Reliability
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Nanofabrication and Lithography Techniques
- Electric Power System Optimization
- Advanced Memory and Neural Computing
- Geotechnical Engineering and Analysis
- Construction Project Management and Performance
- Power System Reliability and Maintenance
- Underground infrastructure and sustainability
- Integrated Energy Systems Optimization
- GaN-based semiconductor devices and materials
- Energy Load and Power Forecasting
- Silicon and Solar Cell Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and interfaces
- Grey System Theory Applications
- Optimal Power Flow Distribution
- Additive Manufacturing and 3D Printing Technologies
- Ga2O3 and related materials
Hohai University
2024
North China Electric Power University
2018-2019
University of California, Los Angeles
2014-2017
In the present era of big data and internet things, use microelectronic products in all aspects our life is manifested by ubiquitous presence mobile devices as i-phones wearable i-products. These are facing need for higher power greater functionality applications such i-health, yet they limited physical size. At moment, software (Apps) much ahead hardware technology. To advance hardware, end Moore's law two-dimensional integrated circuits can be extended three-dimensional (3D ICs). The...
In system level electromigration test of 2.5D integrated circuits, a failure mode due to synergistic effect Joule heating and has been found. the circuit, there are three levels solder joints, two Si chips (one them through-Si-via), one polymer substrate. addition, redistribution layers; between every joints. We found that layer flip chip joints micro-bumps is weak-link failed easily by burn-out in test. The time-dependent with sudden resistance increase. Preliminary simulation results show...
Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found 2.5D integrated circuit (IC) circuit. In IC, a Si interposer was used between polymer substrate and device chip which transistors. The no If transistors are added to the chip, it becomes 3D IC. our test structure, there two chips placed horizontally on interposer. vertical connections through microbumps. We powered one daisy chain of under chip; however, neighboring failed with big holes solder layer....
In system level electromigration test of 2.5D IC, Joule heating enhanced failure has been found to occur in redistribution layer the interposer. our samples, there are two layers (RDL), each between every levels solder joints, so three joints. First, microbumps connect a Si chip on top and an interposer middle. Second, flip solders polymer substrate bottom. Third, BGA balls back as I/O connections outside. tests, ball served cathode allowed electrons flow through circuit path-through-holes,...
With the deregulation of electricity market, generation companies must take part in strategic bidding by offering its quantity and price a day-ahead wholesale market to sell their electricity. This paper studies company with thermal power units wind farms. is assumed be price-maker, which indicates that installed capacity high enough affect market-clearing market. The relationship between then studied. uncertainty considered modeled through set discrete scenarios. A scenario-based two-stage...
As the Moore's law is drawing to an end, there a growing consensus that 3D stacking of Si integrated circuit chips necessary continue current technological trend. In our work, test IC structure successfully achieved and effect filler trap on microbump solder joints will be discussed. samples, two are connected through thermo-compression bonding 20 μm diameter microbumps. After together, some underfill materials found stay interface joining in microbumps; residual defined as "filler trap"....
This paper investigates the thermal cross-talk between powered microbumps under one chip and un-powered neighboring chip. Both chips were on a Si interposer for 2.5D IC. The Joule heating from was found to be transferred laterally along unpowered produced temperature gradient in Void formation is observed both microbumps. latter due thermomigration (TM), former electromigration (EM). amount of voids bigger by TM than EM. void nucleation growing studied examining at different stages during...
This paper addresses the issue of delivering power to high performance 3D stacks such as a processor on cache stack. Through Silicon Vias (TSVs) with their associated keep out zones (KOZ) occupy only small fraction die (<;1%) but can cause much larger design inefficiencies in lower strata. We show that integrating TSVs thin wire levels (M1 for example) hierarchy limits amount current deliverable by TSV well below its capabilities due electromigration limitations level connection TSV. propose...
Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration maturing, reliability parameter to be studied. One such wear-out mechanisms electro-migration (EM). In this paper, we report on experimental electromigration studies of TSVs used in 3-Dimensional (3Di). While themselves can carry large currents, connection on-chip wiring -- so called capture levels both sides thinned die are weakest link from an EM perspective. performance element...
Abstract Delaying responsibility allocation is one of the important contents in construction management power grid infrastructure projects. Due to large investment projects, long period and complicated operation procedures, many delays occurred during process. Based on this, combined with theory time difference theory, this paper proposes a delay analysis method that considers logical relationship between engineering processes. Secondly, route theorem proposed, calculation steps rules...