A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used in differential-type 11-bit SAR ADC. It calibrates the nonlinearities of ADC due to capacitance mismatch as well two parasitic capacitances connected parallel with each bridge capacitor and LSB bank split-CDAC. The does not require any additional analog circuits calibration, because it utilizes one split-CDACs measure error codes other During normal A/D conversion step, 11.5-bit raw code output added...

Purpose Magnetic resonance imaging (MRI) artifacts are originated from various sources including instability of an magnetic (MR) system, patient motion, inhomogeneities gradient fields, and so on. Such MRI usually considered as irreversible, additional artifact‐free scan or navigator is necessary. To overcome these limitations, this article proposes a novel compressed sensing‐based approach for removal artifacts. Theory Recently, the annihilating filter based low‐rank Hankel matrix was...

A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The includes 64 analog front-end branches including non-uniform sampling ADCs, FIFO/Adder, and an on-chip look-up table (LUT). LUT stores the information on rising edge timing of ADC clocks. To include inside chip, size reduced by around 240 times approximating ADC-sample-time profile w.r.t. focal points (FP) along scanline (SL) channel into piece-wise...

To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for ultrasound medical imaging 2D CMUT array. The retrieved successfully two B-mode phantom images steering angle from -45 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> to +45 , maximum delay range of 8 μs, and resolution 6.25 ns. An analog-digital hybrid BF (HBF) chosen utilize easy beamforming operation in digital domain also area by...

Ultrasound imaging is widely used for medical diagnosis, because it harmless to the human body and has real-time processing capability. Usually focusing (beamforming) operation performed both TX RX. The RX by an beamformer [1-5], which consists of delay elements adders. Nowadays, digital beamformers (DBF) are mostly conventional ultrasound high SNR. Recently, 2D transducers have been introduced 3D imaging. Since transducer a huge number (e.g., 9216 72×128 array), cannot use DBF required ADCs...

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and maximum range 768 ns. has focal-point based architecture, which consists 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs RX focusing operation for single focal point. Seven sub-ABFs perform time-interleaving to achieve the Phase interpolators are used in generate sampling clocks with from low frequency system clock 5 MHz. samples 32 echo signals at different times into capacitors,...

This brief presents a compact variable gain amplifier (VGA) with continuous time-gain compensation (TGC) for ultrasound imaging. The proposed VGA utilizes an open-loop topology and transconductance-subtraction load implementation sufficient range. To compensate nonlinearity of VGA, this work proposes systematic predistortion gain-control signal to enhance accuracy TGC operation. implemented in 180-nm CMOS process occupies 0.025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This paper presents an arterial distension monitoring scheme using a field-programmable gate array (FPGA)-based inference machine in ultrasound scanner circuit system. An requires precise positioning of probe on artery as prerequisite. The proposed is based finite state that incorporates sequential support vector machines (SVMs) to assist both coarse and fine adjustments position. SVMs sequentially perform recognitions ultrasonic A-mode echo pattern for human carotid artery. By employing...

A digital-domain calibration is proposed for a split-capacitor DAC of 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The improves the linearity ADC, especially INL by +1.59/-1.71 LSB, SFDR 19.1 dB, and SNDR 5.0 dB (ENOB 0.83 bits). It compensates both mismatch among binary-weighted capacitors errors due to parasitic capacitance bridge-capacitor LSB bank. No extra required in this work, because one two differential branches used measure other branch. Measurements on fabricated chip with 0.13...

A calibration scheme is proposed for a bandgap voltage reference. The calibrates an offset of operational trans‐conductance amplifier (OTA) reference which the critical source output‐voltage deviation based on chopping technique makes output OTA modulate. An infinite impulse response (IIR) filter used to average out modulated OTA. IIR fed into gate node Positive‐channel Metal‐Oxide Semiconductor (PMOS) current located in final branch. As result, becomes insensitive circuit was verified...

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to gate leakage current OTA input transistor, feedback pseudo-resistor conventional ECG moved branch between OP amp summing node DC reference voltage. Also, an circuit with Gm boosting block without reducing...

Abstract A 10‐touch performance is achieved by using a mutual‐capacitive touch sensor. To increase the immunity to display‐generated noise, an integrator used with input node isolated from sensor panel (TSP) during high‐LCD‐noise period, controlled gate‐driver clock. This increases SNR more than 15 dB.

An analytic design guide was formulated for the of 3-stage CMOS OP amp with nested Gm-C(NGCC) frequency compensation. The proposed generates straight-forwardly parameters such as W/L ratio and current each transistor from given specifications, as, gain-bandwidth, phase margin, compensation capacitance to load capacitance. applications this two cases 10pF 100pF capacitances, shows that designed work a reasonable performance in both cases, range 10% 100%

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. VGA has closedloop topology and shows 37-dB-linear characteristic with single-stage amplifier. It consists op-amp, non-binary-weighted capacitor array, gaincontrol block. array reduces the required number capacitors complexity gain-control The been fabricated in 0.35-mm CMOS process. work gives largest range 37 dB per stage, P1 9.5 dBm at 3.3-V among recent circuits available...

Abstract This brief proposes a field programmable gate array (FPGA) based real‐time inference machine for A‐mode ultrasonic echo pattern recognition. The proposed scheme can aid probe positioning of single‐transducer ultrasound devices by detecting specific patterns on scanline. is combination support vector and finite state machine. utilizes minimal pre‐processing feature extraction, considering nature distinctive patterns. In addition, primary computation linear performed sequentially, the...

A current-mode ultrasound beamformer (BF) is proposed. Each channel of BF converts the echo voltage signal into current and performs uniform sampling. The sampled each injected one memory capacitors depending on a delay profile at time instance when sampled. Since multiple currents can be simultaneously added in parallel, parallel shared capacitor. By using this inherent characteristic operation, work has 1D structure unlike 2D other prior BFs. proposed allows simultaneous access from...

This paper proposes a center frequency tracking scheme to optimize pulse-echo response of ultrasonic A-mode scanner. A scanner represents an overall energy conversion characteristic from actuation acquisition. for optimized can be varied depending on voltage, acoustic medium, etc. Most previous methods have focused high-power continuous applications, and relied monitoring phase difference between actuating voltage current with auxiliary sensors. work focuses peak envelope echo without...

This work proposes a proof-of-concept ultrasound blood-flow-monitoring circuit system using single-element transducer. The consists of ultrasonic transducer, an analog interface circuit, and field-programmable gate array (FPGA). Since the uses image cannot be reconstructed unless scanning with mechanical movement is used. An blood-flow monitor basically needs to acquire Doppler sample volume by positioning range at vessel region on scanline. Most recent single-transducer-based pulsed-wave...

This paper presents a programmable gain amplifier (PGA) with fast transient response for medical ultrasound system. In this real-time control of PGA, image artifacts can occur during gain-switching period. To sufficiently reduce period due to switching work proposes preset scheme capacitors and single-stage push-pull amplifier. The preliminarily set the operating points TX phase system, so point fluctuation is minimized. addition, recovery be achieved by adopting flipped voltage follower...

The size of the look-up-table to store ADC sample-times was reduced by around 200 times implement a single-chip non-uniform-sampling 32-channel digital-beamformer for ultrasound medical imaging. It achieved storing 2nd derivatives w.r.t. focal point numbers on scanline. proposed includes LUT, sample clock generators ADCs, LNAs, VGAs, and DBF in single-chip. A 15-dot image successfully reconstructed chip with simulation.

A sample clock generator (SCG) for application in a 32-channel ultrasound receiver beamformer is proposed. The RX samples the echo signals at delayed timings to align them time domain before summing them. proposed SCG employs dual counter and comparator scheme generate sampling clocks with 4.17 ns delay control resolution. implemented using Verilog RTL code analog block of was modeled ideal hold circuits. simulated mixed-signal simulator results verify feasibility scheme.

This paper proposes an ultrasonic echo-signal based digital background calibration technique for a pipelined SAR ADC. The proposed ADC adaptively compensates code-step error between two adjacent code segments by using gradient-decent optimization algorithm. It monitors harmonics power of echo signal in output and tracks the optimal step minimum power. 10-bit 11-MS/s was fabricated 0.18-㎜ CMOS process. scheme implemented with FPGA. In measurement, tracked applying signal. single-tone...

Photoacoustic (PA) imaging is a high-fidelity biomedical technique based on the principle of molecular-specific optical absorption biological tissue constitute. Because PA shares same basic as that ultrasound (US) imaging, use PA/US dual-modal can be achieved using single system. However, because limited to shallower depth than US due extinction in tissue, signal yields lower signal-to-noise ratio (SNR) images. To selectively amplify signal, we propose switchable preamplifier for...

Sources of noise that corrupt the reference level VREF during a ramp ADC operation are identified and analyzed. For power analysis, PSR bandgap current generator investigated through small signal circuits. device appearing at level, contribution from each is expressed in terms design variables. The variables arranged table to serve as guide for low CMOS imager design.