A5041134555- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Parallel Computing and Optimization Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Data Storage Technologies
- Advancements in Battery Materials
- Low-power high-performance VLSI design
- Error Correcting Code Techniques
- Semiconductor materials and devices
- Advanced Battery Technologies Research
National University of Defense Technology
2021-2024
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard achieve immunity from a Single Event Upset (SEU), even when ~3-µm well isolation utilized. SEU mitigation of hardened DFFs was affected by data patterns clock signals due imbalance in number...
This paper discusses the stuck bits induced by gate breakdown of PMOS in sub-20 nm FinFET static random access memory (SRAM) device. After heavy-ion experiment, several are SRAM matrix, which cannot be set or reset. To investigate factors that caused bit, we perform electrical failure analysis (EFA) to measure electric characteristics transistors and normal cells separately. The measurement results show a clear at pull-up (PPU) transistor all measured cells. Meanwhile, SPICE simulation based...
The convergence of High-Performance Computing (HPC) and Artificial Intelligence (AI) has become a promising trend. Due to the different computation patterns HPC AI applications, it's challenging design an appropriate architecture balance their demand. To address this, we propose Matrix Zone (MZ), enhanced Systolic Array-based matrix engine that accelerates General Multiplication (GEMM) for both applications. We develop semi-memory hierarchy reduce on-chip area consumption data stitching...
Abstract Traditionally, it is believed that only reverse biased PN junctions can collect ionized electron-hole pairs. Therefore, the drain of transistor in off-state be considered as a sensitive node, which easy to absorb charge and cause upset. This paper finds on-state transistors also become nodes. studies relationship between SEU order flip-flop layout. It found adjacent placement promote occurrence SEU, targeted hardened plan proposed. The results this are helpful for design...
Abstract The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field anti-irradiation. Based 3D-TCAD simulation, sensitivity SET 28-nm bulk devices studied. simulation results show that electrical characteristics device shows an anti-temperature effect, but worst case still occurs at high rather than low temperature. triple-well structure also N+ deep well can significantly increase when hitting NMOS and enhance width. research content...