A5039313883- Radiation Effects in Electronics
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Advancements in Semiconductor Devices and Circuit Design
- Particle Detector Development and Performance
- Ion-surface interactions and analysis
- Advanced Photocatalysis Techniques
- ZnO doping and properties
- Carbon Nanotubes in Composites
- Advanced Data Storage Technologies
- Ga2O3 and related materials
- Radiation Detection and Scintillator Technologies
- Radiation Therapy and Dosimetry
- Low-power high-performance VLSI design
- Interconnection Networks and Systems
- 3D IC and TSV technologies
- CCD and CMOS Imaging Sensors
- Graphene research and applications
Chinese Academy of Sciences
2018-2025
Institute of Modern Physics
2018-2025
University of Chinese Academy of Sciences
2018-2020
Swift heavy Ta ions with an ultra-high energy of 2896 MeV are utilized for irradiation β-Ga2O3 photodetectors. Noteworthy variations in device performance under different wavelengths observed. Under 254 nm light illumination, the photocurrent devices exhibit degradation at low ion fluences but gradually recover and even surpass non-irradiated fluence 1 × 1010 cm−2. Conversely, 365 increases slightly decreases same high Cathodoluminescence spectra first-principles calculations elucidate...
Recent advances in carbon nanotube (CNT)-based integrated circuits have shown their potential deep space exploration. In this work, the mechanism governing heavy-ion-induced displacement damage (DD) effect semiconducting single-walled CNT field transistors (FETs), which is one of factors limiting device robustness space, was first and thoroughly investigated. FETs irradiated by a Xe ion fluence 1012 ions/cm2 can maintain high on/off current ratio, while transistors' performance failure...
The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded (EBRAMs) flip-flops. This hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that CRAMs had a high linear energy transfer threshold of upset ∼18...
The standard and layout-hardened D filp-flops (DFFs) named DFF1-6 were designed manufactured based on an advanced 22-nm ultrathin body buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. Heavy-ion irradiation results indicate that FD-SOI technology has contributions to radiation hardness the hardened DFFs have higher single-event upset (SEU) tolerance than DFF. upsets induced by embedded SET targets are strongly dependent testing frequency. layout separating dual...
Radiation effects can induce severe and diverse soft errors in digital circuits systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity promote space application of ultra large-scale integrated (ULSI). Picosecond pulsed laser high energy heavy ions were employed for irradiation. Before tests, SRAM-based configure RAMs (CRAMs) initialized configured. The 100% embedded block...
Geant4 Monte Carlo simulation results of the single event upset (SEU) induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported. The SEU cross section for planar and three-dimensional (3D) die-stacked SRAM calculated. show that sections device 3D different each other under low proton direct ionization mechanism, but almost same high proton. Besides, multi-bit (MBU) ratio pattern presented analyzed. indicate MBU is higher than device, patterns more complicated. Finally,...
This paper discusses the stuck bits induced by gate breakdown of PMOS in sub-20 nm FinFET static random access memory (SRAM) device. After heavy-ion experiment, several are SRAM matrix, which cannot be set or reset. To investigate factors that caused bit, we perform electrical failure analysis (EFA) to measure electric characteristics transistors and normal cells separately. The measurement results show a clear at pull-up (PPU) transistor all measured cells. Meanwhile, SPICE simulation based...
The total ionizing dose (TID) effects on single-event upset (SEU) hardness are investigated for two silicon-on-insulator (SOI) static random access memories (SRAMs) with different layout structures in this paper. contrary changing trends of TID SEU sensitivity 6T and 7T SOI SRAMs observed our experiment. After 800 krad(Si) irradiation, the cross-sections increases by 15%, while decreases 60%. Experimental results show that not only affected but also strongly correlate structure memory cells....
Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between well boundary and N-channel metal–oxide semiconductor (NMOS) transistor or P-channel (PMOS) can mitigate cross section of single event upset (SEU) in 14-nm complementary (CMOS) bulk FinFET technology. The competition charge collection sensitive nodes, enhanced restoring currents change bipolar effect are responsible for decrease SEU section. Unlike dual-interlock cell (DICE) design, this approach is more...
Three-dimensional integrated circuits (3D ICs) have entered into the mainstream due to their high performance, integration, and low power consumption. When used in atmospheric environments, 3D ICs are irradiated inevitably by neutrons. In this paper, a die-stacked SRAM device is constructed based on real planar device. Then, single event upsets (SEUs) caused neutrons with different energies studied Monte Carlo method. The SEU cross-sections for each die whole three-layer obtained energy...
This article concerns the top silicon layer thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {SOI1}}$ </tex-math></inline-formula> ) and back-gate bias dependence of single event upset (SEU) cross section in notation="LaTeX">$0.18 ~\mu \text{m}$ double-silicon-on-insulator (DSOI) static random access memory (SRAM) through high linear energy transfer (LET) heavy ions experiments. The...
DICE hardened configuration logics in million-gate FPGA were investigated. The rectangular parallel-piped models established based on the material details and layout of FPGA. Multiple sensitive volumes charge collection weights ascertained. simulations matched further explained our heavy ion experiments.
The interaction of radiation with three-dimensional (3D) electronic devices can be determined through the detection single-event effects (SEU). In this study, we propose a method for evaluation SEUs in 3D static random-access memories (SRAMs) induced by heavy-ion irradiation. cross-sections (CSs) different tiers, as function linear energy transfer (LET) under high, medium, and low irradiation, were obtained Monte Carlo simulations. simulation results revealed that maximum value CS was...