Liewei Xu

ORCID: 0000-0002-8422-3409
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About
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Research Areas
  • Radiation Effects in Electronics
  • Semiconductor materials and devices
  • VLSI and Analog Circuit Testing
  • Low-power high-performance VLSI design
  • Advancements in Semiconductor Devices and Circuit Design
  • Reliability and Maintenance Optimization
  • Brain Tumor Detection and Classification
  • Parallel Computing and Optimization Techniques
  • Advanced Neural Network Applications
  • Neural Networks and Applications
  • Integrated Circuits and Semiconductor Failure Analysis
  • Interconnection Networks and Systems
  • Embedded Systems Design Techniques

Fudan University
2019-2021

Shanghai Fudan Microelectronics (China)
2017-2021

Xinjiang Technical Institute of Physics & Chemistry
2018

Chinese Academy of Sciences
2018

This paper investigates the total ionizing dose (TID) responses of forward body bias (FBB) ultrathin and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) transistors, which are commonly used in commercial foundries. The experimental results demonstrate that TID-induced threshold voltage shift FBB nMOSFET cannot be mitigated by applying biasing to back-gate (back-gate biasing). Bias condition dependence has also been explored, revealing building up oxide-trapped charge (Not) is...

10.1109/tns.2019.2901755 article EN IEEE Transactions on Nuclear Science 2019-02-26

Radiation effects can induce severe and diverse soft errors in digital circuits systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity promote space application of ultra large-scale integrated (ULSI). Picosecond pulsed laser high energy heavy ions were employed for irradiation. Before tests, SRAM-based configure RAMs (CRAMs) initialized configured. The 100% embedded block...

10.3390/electronics8121531 article EN Electronics 2019-12-12

With device scaling-down, circuits appear more susceptible to transient faults especially for the bulk silicon process. Thus, FD-SOI technology has been widely popular in serious radiation environment due its high radiation-tolerance inherence created by an additional BOX layer. In this work, seven different inverter chains with two kinds of core voltages, four channel areas and a stack chain are designed investigate SET advanced 22 nm CMOS technology. A NAND is also used comparison chains....

10.1109/access.2020.2978201 article EN cc-by IEEE Access 2020-01-01

The influence of total ionizing dose (TID) irradiation on hot-carrier effect short channel ultra-thin body and buried oxide Fully Depleted Silicon On Insulator (UTBB FD-SOI) n-MOSFETs is investigated. Experimental results show larger parameters degradation for irradiated devices, which due to generated defects in (BOX).

10.1109/nsrec.2018.8584318 article EN 2018-07-01

A flexible and multipurpose Single Event Effects (SEEs) testing system was developed for evaluating the reliability of nanoscale Very Large Scale Integrated Circuit (VLSI). The accurate detection, comparation classification latch-up, upset, functional interrupt were achieved. In host PC part, two customized software systems developed, including Procise maximal resources occupation a C# based visual control interface real-time communication. For hardware, motherboard-daughterboard guaranteed...

10.1587/elex.16.20190196 article EN IEICE Electronics Express 2019-01-01

10.1016/j.nima.2021.165618 article EN Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment 2021-07-08

In this paper, the body bias in 28nm Bulk and back 22nm FDSOI are analyzed compared from two aspects: power consumption circuit performance. Taking a 65-stage ring oscillator (RO) with 4-level frequency divider as an example, transistor lengths all set to 30nm, post simulation results show that, for 22FDX RO, operating can adjust 57.8MHz 206MHz, current varies 24uA 91uA; while 28HPC, bulk RO only modulate 92.8MHz 127MHz, 67.8uA 129uA. Therefore, both view of performance, ability circuits...

10.1109/s3s.2017.8309225 article EN 2017-10-01

In this study, we propose a software-hardware combined solution for efficient sparse neural network computing. Much of the connections between each layers are pruned in network. Usually weights compressed format, but corresponding feature map data need to be pared before passing computation engine. Since require indirect memory access, there needs large amount multiplexers locate position. Motivated by this, new architecture with much smaller selection multiplexer design. our hardware...

10.1145/3289602.3293952 article EN 2019-02-20
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