A5090206630- GaN-based semiconductor devices and materials
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies
- Ga2O3 and related materials
- Silicon Carbide Semiconductor Technologies
- Analog and Mixed-Signal Circuit Design
- Advanced Photonic Communication Systems
- Advancements in Semiconductor Devices and Circuit Design
- Optical Network Technologies
- Advanced Optical Network Technologies
- Electromagnetic Compatibility and Noise Suppression
- Low-power high-performance VLSI design
- Microwave Engineering and Waveguides
- Semiconductor Lasers and Optical Devices
- VLSI and Analog Circuit Testing
- Semiconductor Quantum Structures and Devices
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- Advanced Power Amplifier Design
- VLSI and FPGA Design Techniques
- Machine Fault Diagnosis Techniques
- Extraction and Separation Processes
- Metal and Thin Film Mechanics
- Semiconductor materials and interfaces
Pennsylvania State University
2019-2024
Pohang Iron and Steel (South Korea)
2024
Hongik University
2012-2021
Sungkyunkwan University
2018-2021
Kyma Technologies (United States)
2021
Park University
2020
Korea University
2015-2016
Sogang University
2008-2012
SK Communications (South Korea)
2008-2009
Georgia Institute of Technology
1997-2005
This article reports on two generations of GaN-on-sapphire super-heterojunction (SHJ) transistors, aiming at the realization 10-kV class power transistors with low static and dynamic ON-resistance. First generation (Gen. 1) GaN SHJ-FETs used a single 2-D electron gas (2DEG) channel design Schottky gate. Experimental results indicated feasibility achieving blocking, however, room for improvement to reduce source-to-drain ON-resistance <inline-formula...
Presents design, implementation, and measurement of a three-dimensional (3-D)-deployed RF front-end system-on-package (SOP) in standard multi-layer low temperature co-fired ceramic (LTCC) technology. A compact 14 GHz GaAs MESFET-based transmitter module integrated with an embedded bandpass filter was built on LTCC 951AT tapes. The up-converter MMIC voltage controlled oscillator (VCO) exhibits measured up-conversion gain 15 dB IIP3 dBm, while the power amplifier (PA) shows 31 1-dB compression...
We have developed a silicon oxynitride (SiON) deposition process using plasma-enhanced chemical vapor system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had relative constant 5.3 and breakdown field 12 MV/cm. A normally-off MISFET fabricated with 33-nm exhibited threshold voltage ~2 V, an ON-resistance 7.85 mQ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present a systematic study on the design of novel GaN/AlGaN/GaN super-heterojunction Schottky diode. Through physics-based TCAD simulation, we discuss three important aspects: 1) how to structure form high-density 2-D electron gas and scale it multiple vertically stacked channels with less risk in reaching critical thickness limited by strain epitaxy; 2) reach charge balance sensitive is breakdown voltage respect doping imbalance; 3) ensure that processes depleting accumulating electrons...
We have developed a novel unidirectional AlGaN/GaN-on-Si heterojunction field-effect transistor (HFET) with reverse blocking drain. A recessed Schottky contact was incorporated into conventional ohmic drain electrode to prevent the undesired current flow while reducing turn-on voltage in forward characteristics. The combination of and electrodes significantly reduced comparison 0.4 V, an off-state breakdown 615 −685 V were achieved for gate-to-drain distance 12 µm.
In this study, we investigated the process-dependent dynamic on-resistance [RDS(on)] characteristics of recessed AlGaN/GaN-on-Si metal–oxide–semiconductor heterojunction field-effect transistors with a SiO2 gate oxide. order to improve RDS(on) characteristics, processing technology was carefully optimized, including post-metallization annealing and field plate formation. A threshold voltage 2.0 V achieved breakdown 1070 V. The fabricated device exhibited DC 5.22 mΩ·cm2 very stable i.e., less...
This letter reports an experimental demonstration of charge-balanced GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs). Charge balance between the n-type delta-doping and p-type doping was achieved by adjusting thickness pGaN. device structure enabled scaling breakdown voltage to over 3 kV, dynamic switching up 2.8 kV without using any field-plate.
A new all-digital multiplying delay-locked loop (MDLL) is presented that can provide programmable fractional-ratio frequency synthesis of a de-skewed clock. The proposed MDLL (FMDLL) employs select logic for controlling three operation modes and utilizes phase-detecting structure to achieve inherent cancellation the internal phase offset. digital FMDLL implemented in 65-nm 1-V CMOS process occupies an area 0.019 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present a fully monolithic X-band VCO MMIC implemented in commercial GaAs MESFET process. Measurement results demonstrate single sideband phase noise of -91 dBc/Hz at 100 KHz offset. This achieves maximum output power 11.5 dBm with 12 dB control and 550 MHz frequency tuning range. Second harmonic suppression 20 or more is measured across the entire These are comparable to, better than, best reported VCO's high electron mobility transistor (HEMT) heterojunction bipolar (HBT) processes.
We report experimental and analytical results of a fiber-optic link that supports simultaneous transmission baseband data subcarrier multiplexed control-data channels. A novel transmitter design is used to optoelectronically combine channels onto the optical carrier using differential Mach-Zehnder (MZ) interferometer modulator. Microwave direct detection channel simplifies receiver network architecture. An approach optimize parameters for given transmitter/receiver configuration presented,...
Negative bias temperature instability (NBTI) has become a major factor of reliability. In this paper, we proposed simple analytical model to predict the degraded delay distribution due NBTI and process variation. Using our variation-aware timing analysis framework, accurate gate is computed without tedious simulation. Moreover, conventional design techniques can apply develop reliable circuit using model.
This paper presents a 680 MHz-6 GHz 2 x multiple-input and multiple-output (MIMO) long-term evolution (LTE) RF transceiver in 65-nm CMOS for low-cost multi-band capable femtocell base stations. The integrates two receivers (RXs), transmitters (TXs), frequency synthesizers, the 2x MIMO operation to support both division duplex (FDD) time (TDD) modes. Each pair of an RX TX features eight single-ended low noise amplifiers (LNAs), outputs that extensively share active passive circuits with...
We have developed a low-temperature ohmic contact process with recessed overhang configuration for Au-free (complementary metal-oxide semiconductor) CMOS-compatible AlGaN/GaN heterostructure field effect transistors (HFETs). The has Ti/Al bilayer directly in the heterojunction interface at sidewall overlaid AlGaN barrier layer, which allows good and reproducible formation annealing. optimum thickness was 40/200 nm, resulted an Rc of 0.76 Ω mm excellent surface morphology when annealed 550 °C...
This article reports GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs) with substantially improved performance. Metal-2DEG sidewall n-ohmic contacts were deployed to achieve low contact resistance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.75~\Omega ~ \cdot ~mm$ </tex-math></inline-formula> , avoiding the risk abnormally high caused by inaccurate etch depth control. A pGaN notch formed...
This letter reports the first controlled experimental study on impact of charge-balance static and dynamic characteristics GaN super-heterojunction Schottky barrier diodes (SHJ-SBD). Charge balance between p- n-type doped for reducing peak E-field can be optimized via etching (CBE) p-GaN SHJ region to improve <inline-formula> <tex-math notation="LaTeX">${R}_{\textit {ON}}$ </tex-math></inline-formula> degradation breakdown voltage (BV). Three CBE conditions were fabricated with same process...
As CMOS devices become smaller, process and aging variations a major issue for circuit reliability yield. In this paper, we analyze the effects of on such as hot carrier injection (HCI) negative bias temperature instability (NBTI). Using Monte-Carlo based transistor-level simulations including principal component analysis (PCA), correlations between are considered. The accuracy is improved (2-7%) compared to other methods in which ignored, especially smaller technologies.
A new programmable delay‐locked loop (DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL‐based generators that generate only integer multiplication, the proposed provides fractional‐ratio multiplication while maintaining advantages of DLLs, such as deskewing between input and output clocks. Implemented in a 0.13 µm 1.2 V CMOS process, achieves an effective peak‐to‐peak jitter 7.5 ps occupies active area 0.018 mm 2 dissipating 9.0 mW at...
Stator-slot magnetic wedges are used instead of conventional epoxy glass in large, high-output induction motors since the motor efficiency and power factor can be improved. However, cases loose or missing due to their weak mechanical strength have recently been increasingly reported. Although deteriorate performance reliability, there is currently no test method accepted field for wedge quality assessment other than offline, disassembled visual inspection. In this paper, a new in-service...
Abstract The present study investigated the Mg doping effect in gallium nitride (GaN) buffer layers (BLs) of AlGaN/GaN high-electron-mobility transistor (HEMT) structures grown on semi-insulating 4H-SiC substrates by metal organic chemical vapor deposition. When concentration was increased from 3 × 10 17 to 8 18 cm −3 , crystal quality slightly deteriorated, whereas electrical properties were significantly changed. leakage approximately 50 times 0.77 39.2 nA at −50 V with concentration....
Due to the difficulty of GaN epitaxy growth on Si(001) substrate, GaN-on-Si wafers are generally grown Si(111) substrates. Because poor electrical characteristics orientation, monolithic integration between CMOS ICs and devices cannot be implemented GaN-on-Si(111) wafers. At this point view, Si(110) substrate will an alternative choice for growth, because it has good atomic arrangement with AlN seed layer advantage excellent hole mobility over Si(001). We have developed high quality...
We have developed an AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET) based bidirectional switch with embedded diode bridges for power switching applications. Four Schottky barrier diodes were in AlGaN/GaN MOSHFET to minimize the parasitic elements and thus reduce chip area. The fabricated device functioned as a normally OFF, switch, where gate threshold voltage was ~1 V both forward reverses modes. maximum drain current density reverse operation...
This paper presents a 10 Gbps serializer/deserializer (SerDes) with phase interpolator (PI) based clock and data recovery (CDR) circuit for high-speed short-range wireless chip-to-chip communication. The SerDes performs 4:1 muxing 1:4 demuxing functions. PI-based CDR uses an 8-phase delay-locked loop (DLL) to produce set of evenly spaced reference phases. vernier, then transforms the 8-phases sampling clocks sampler, which 2× oversampling recover from input signal. Implemented in 65 nm CMOS...
As CMOS devices become smaller, process and aging variations a major issue for circuit reliability yield. In this paper, we analyze the effects of on such as hot carrier injection (HCI) negative bias temperature instability (NBTI). Using Monte-Carlo based transistor-level simulations including principal component analysis (PCA), correlations between are considered. The accuracy is improved (2-7%) compared to other methods in which ignored, especially smaller technologies.
As CMOS devices become smaller, the process variations (PVs) and aging (AVs) major issues for circuit reliability yield. In this paper, we analyze effects of PVs on such as hot carrier injection (HCI) negative bias temperature instability (NBTI). Using Monte Carlo-based transistor-level simulations including principal component analysis, correlations between AVs are considered, by which accuracy analysis is improved (1.2% standard deviation 1.7% Vth <sub...