A5101820643- Semiconductor materials and devices
- Advanced Data Storage Technologies
- Silicon Carbide Semiconductor Technologies
- Electrostatic Discharge in Electronics
- Advancements in Semiconductor Devices and Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Advanced Memory and Neural Computing
- Magnetic properties of thin films
- Copper Interconnects and Reliability
- Cellular Automata and Applications
- Photonic and Optical Devices
- Nanowire Synthesis and Applications
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor Lasers and Optical Devices
- Optical Network Technologies
Technical University of Munich
2025
Macronix International (Taiwan)
2008-2023
National Tsing Hua University
2005-2008
We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in 3D vertical channel and charge-trapping NAND flash cell string. characterize RTN read current each string at different pass voltages. characteristics resulting from or are differentiated. A method to identify is proposed. perform TCAD simulation calculate electron density Measured can be explained by current-path percolation carrier screening effects. The distribution amplitudes strings characterized.
A variable-amplitude low-frequency charge-pumping technique is proposed to characterize the nitride-trap energy and spatial distributions in SONOS Flash memory cells. numerical model based on Shockley-Read-Hall-like electron tunneling capture used correlate a current with position. By changing frequency pulse amplitude measurement, density, as function of trap position energy, can be extracted.
The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, width seldom specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract intrinsic of devices, and split capacitance-voltage method mobility with various channel widths. Although it known that under influence compressive STI both NMOS PMOS will degrade decreasing width, first...
We investigate a hot-carrier injection-induced program disturb in 3D NAND flash memory. As there exist specific coding patterns, "down-coupling" region and "pre-charge" regions are formed during program-verify the following phases, respectively, inhibit cell strings. A high heating field is built nearby PGM wordline. Hot carriers may inject into cells as Vpgm applied. Soft ramp-down pre-turn-on schemes proposed to mitigate this disturb.
For 3D NAND memory, with continuous word line (WL) pitch scaling, deteriorated WL interference and the impact on triple-level cell (TLC) operation window are anticipated. However, as is scaled from 63nm to 50nm, enormous Vt losses induced by significantly found. With pitch, non-linear behavior of increasing programmed neighboring aggressor occurs earlier, which leads unacceptable TLC losses. The due insufficient gate overdrive cell, reduction originates weakly-inverted channel locating at...
Starting from CIEF (charge injection induced errors) CBCM (charge-based capacitance measurement), a novel method free the errors by charge-injection is developed. This used for first time to investigate impact of floating dummy-fills on interconnect capacitance, in practice. The confirmed play an important role successful circuit design. Besides, guideline optimize chip performance and minimize crosstalk dummy pattern design also proposed this paper.
In this letter, the word line (WL) interference behavior in 3D NAND cell and impact on program sequence of array operation are discussed. The WL induced by source-side neighboring is always smaller than that drain-side cell. Due to asymmetric characteristic, from top bottom will have advantage suffering less window loss resulting interference, over traditional top. This can be clearly validated experimental results. However, at some specific WL’s array, trend reversed. root cause reverse...
In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in NAND Flash peripheral circuit. Such DN device needs to sustain highest voltage (>30V) during programming. We observed product chip. Electrical measurement shows that first measured (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</sub> ) from virgin state is usually lower than after stress, which called "walk-out" effect. The...
An enhanced PMOS-triggered PMLSCR is proposed. Under the condition that both PNP and NPN BJT's are triggered simultaneously, voltage overshoot turn-on uniformity can be further improved. From TCAD simulation, it clear with help of trigger current, conduction path SCR goes deeper snapback reduced. By designed power sequence, holding current devices considering self-heating effect attained. Robust EOS immunity assured accordingly.
Coupling interference from adjacent cells of conventional floating gate structure has become a main limiting factor the scalability NAND-type flash memory (J. Lee et al., 2002). The better immunity against issue is always considered as advantage nitride-storage memory, which been another mainstream non-volatile because its easy integration and two-bit storage capability (B. Eitan, 2000), (W.J. Tsai 2001). However, it disclosed that similar still exists in wordlines close enough (Y.W. Cheng...
Impact of threshold voltage (Vt) level from the cells at neighboring word-lines (WLs) on random telegraph noise (RTN) in floating-gate (FG) NAND flash memory is investigated. Due to aggressive pitch scaling, two-step programming utilized suppress cell-to-cell interference and achieve multi-level-cell (MLC) operation [1,2]. Such scheme could compromise get optimized Vt distributions selected WL (sel-WL) even if adjacent WLs reveal various states. Once keeps low-Vt state, a compact RTN...
In this paper, a compact SPICE model of NAND strings especially for program inhibit operation is proposed. With the addition 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order capacitances and GIDL current, capacitive boosting with Vpgm Vpass, potential lowering due to current generated at GSL edge can be well considered in model.