A5082109806- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Data Storage Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in Photolithography Techniques
- Industrial Vision Systems and Defect Detection
- Advanced Surface Polishing Techniques
- Copper Interconnects and Reliability
- Electron and X-Ray Spectroscopy Techniques
- Silicon and Solar Cell Technologies
- Thin-Film Transistor Technologies
- Metal and Thin Film Mechanics
- Plasma Diagnostics and Applications
- Advanced Memory and Neural Computing
- 3D IC and TSV technologies
- Electronic and Structural Properties of Oxides
- Diamond and Carbon-based Materials Research
- Surface Roughness and Optical Measurements
- Silicon Carbide Semiconductor Technologies
- Advanced materials and composites
- Magnetic properties of thin films
- Semiconductor materials and interfaces
- Cellular Automata and Applications
- Advanced Machining and Optimization Techniques
- Electrostatic Discharge in Electronics
Macronix International (Taiwan)
2015-2024
China Medical University
2021-2024
Temple University
2024
Harvard University
2024
American Academy of Otolaryngology — Head and Neck Surgery
2024
China Medical University Hospital
2021
Chang Gung Memorial Hospital
1998-2019
Chang Gung University
2019
Macronix International (China)
2011-2014
National Tsing Hua University
2014
A bandgap engineered SONOS with greatly improved reliability properties is proposed. This concept demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin "O1/N1/O2" serves as non-trapping tunneling dielectric, N2 high-trapping-rate charge storage layer, and O3 blocking oxide. The provides "modulated barrier" - it suppresses direct at low electric field during retention, while allows efficient hole erase high due to band offset. Therefore, this BE-SONOS offers fast...
An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of NAND, it also allows junction-free structure which particularly important for stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, first time "Z-interference" between adjacent vertical layers studied. The proposed VG better X, Y pitch scaling...
Abstract Loss of heterozygosity (LOH) was examined at 86 loci distributed on every chromosomal arm in 50 human ovarian tumors. Frequent allele losses were observed chromosomes 13q (42%), 17p 17q (45%), and Xp (41%). Deletion mapping chromosome 17 revealed a candidate gene the long distal to D17S41/S74 for cancer which is distant from locus early onset breast cancer. LOH found be concordant with 3p, 13q, suggesting that it may an event neoplastic development. These findings indicate multiple...
A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) memory. device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -poly gate integrated a NAND array. Small devices (L/W=0.2/0.09 mum) excellent performance reliability properties are achieved. The...
We investigated electric field-induced trapped electron lateral migration in a SONOS flash cell. The threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) and gate-induceddrain leakage (GIDL) current were measured to monitor nitride movement retention. applied different voltages the gate source/drain retention vary vertical fields. Our study shows that: 1) GIDL can be used charge 2) exhibits strong dependence on...
Theoretical calculation indicates that when the fin width is comparable to EOT of ONO, bottom oxide electric field around tip significantly increased, resulting in enhanced program/erase efficiency. We also discover non-uniform injection along changes DC characteristics (S.S. and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) during program/erase, effective channel FinFET SONOS only tip. integrate BE-SONOS a body-tied structure with...
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive 20nm 2D NAND. In this work, we propose a gate (VG) using self-aligned independently controlled double (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty cell size increase, making our VG as scalable conventional We present world's first <; 50nm...
The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the can cause abnormal subthreshold current during programming. Careful well doping optimization necessary to suppress parasitic leakage path avoid behavior. Second, significantly changes P/E speed degrades...
Reliability properties of bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) are extensively studied. First, the erase mechanism BE-SONOS is confirmed as substrate hole tunneling through ultra-thin ONO dielectric. Next, very long-term (>3,000 hours) high-temperature baking data (from 150 to 250degC) for various programmed/erased states and cycling history collected analyzed a thorough understanding retention property. By transforming (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states a nor-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept this use RTS extract an oxide trap position channel then as internal probe detect local potential change resulting from during program/erase. By using method, width charge-induced barrier shown be around 20 nm hot electron (CHE) program. Our also confirms that Channel Initiated...
The longitudinal relationship between central plastic changes and clinical presentations of peripheral hearing impairment remains unknown. Previously, we reported a unique pattern "healthy-side dominance" in acute unilateral idiopathic sudden sensorineural loss (ISSNHL). This study aimed to explore whether such hemispheric asymmetry bears any prognostic relevance ISSNHL along the disease course. Using magnetoencephalography (MEG), inter-hemispheric differences peak dipole amplitude latency...
Pattern dependent charging effect is explored in this study. Due to increased film thickness 3D NAND structure, a derivative problem-the plasma-induced damage enhanced during high aspect ratio (HAR) etching. In paper, several effective methods are demonstrated alleviate the impact of profile distortion due while etching (>14) trenches.
Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. Furthermore, slurries or other consumable parts, like PAD and Disks selection are the keys for CMP optimization. The most difficult thing in is have capability predict cover various topologies layout densities patterned wafers preventing hot spots occurrences. In this study, different Neural-Network...
Sub-30nm TFT CT NAND flash devices have been extensively studied. Although were often believed to much worse performance than bulk devices, our results show that as scale down sub-30nm, the DC characteristics (such read current and subthreshold slope (S.S.)) approach those of because sub-30 nm contain no grain boundaries. The memory window is also larger planar due tri-gate structure enhances electric field during programming/erasing. However, a fair percentage boundaries with poorer S.S. g...
This study explores the relationship between both physical and electrical characteristics of silicon oxynitride (SiON) films refractive index. The single wafer rapid thermal process modules were used for low pressure chemical vapour deposition SiON films. A series with index 1.50 1.83 fabricated. Fourier transform infrared absorption spectroscopy x-ray photoelectron identified bonding configurations different films: Si–N bonds are replaced by Si–O as declines. Moreover, Si atomic ratio is...
Scaling of the planar thin FG NAND device down to 20nm is experimentally studied for first time. Using a (<10nm) and barrier engineered CT IPD showed reasonable memory window endurance, but overall significantly degraded compared longer channel devices. Through detailed 3D TCAD simulations we find that edge fringing field plays dominant role in degradation. The conventional short-channel Vt roll-off effect also induces significant programmed-state subthreshold slope (S.S.) degradation...
Unlike the floating gate Flash device, charge-trapping (CT) devices store charges locally and are thus profoundly affected by non-uniform injection effect. The characteristics of a CT device dominated local minimum-Vt region along channel width. We have analyzed various STI structures including raised-STI, recessed-STI, near-planar structures, found that program/erase strongly impacted corner geometry due to field enhancement (FE) effects. Moreover, both gm S.S. vary during increase...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, the reliability properties of bandgap-engineered SONOS (BE-SONOS) devices with various processing methods are extensively studied. BE-SONOS employs a multilayer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as tunneling barrier that provides an efficient hole-tunneling erase but eliminates direct-tunneling leakage. can overcome fundamental limitation conventional SONOS, for which...
We have successfully developed a 128Gb MLC (or 192Gb TLC) 3D NAND Flash using 16-layer SGVC architecture. The produced memory density is 1.6 Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for or 2.4 TLC (including CMOS peripheral area, spared BL's and blocks). Such comparable to 48-layer the popular gate-all-around (GAA) structures. has important advantage of much smaller cell size pitch scaling capability which allows very...