A5003335165- Electrostatic Discharge in Electronics
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- 3D IC and TSV technologies
- Electromagnetic Compatibility and Noise Suppression
- GaN-based semiconductor devices and materials
- Thin-Film Transistor Technologies
- Advanced Photonic Communication Systems
- Optical Network Technologies
- Electronic Packaging and Soldering Technologies
- Advanced Data Storage Technologies
- Photonic and Optical Devices
- Radio Frequency Integrated Circuit Design
- Laser Design and Applications
- Advanced Sensor and Energy Harvesting Materials
- Silicon Carbide Semiconductor Technologies
- Cellular Automata and Applications
- Non-Invasive Vital Sign Monitoring
- Silicon and Solar Cell Technologies
- Advanced Image Fusion Techniques
- Advanced Fiber Optic Sensors
- Semiconductor Lasers and Optical Devices
- Semiconductor Quantum Structures and Devices
- Image Processing Techniques and Applications
IMEC
2015-2024
National Cheng Kung University
2024
National Chin-Yi University of Technology
2024
Analog Devices (United States)
2023
Universität der Bundeswehr München
2023
Shanghai Institute for Science of Science
2023
Victoria University of Bangladesh
2023
MIT World Peace University
2023
National Taiwan University
2023
University of Illinois Urbana-Champaign
2023
We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL pitch=75nm, 64-WL string 63% array core efficiency. This is the first time that a can be successfully scaled to below 3Xnm in one lateral dimension, thus stack device already provides very cost effective technology lower than conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve manufacturability layout twists even/odd BL's (and pages) opposite direction (split-page BL)...
This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology the fifth generation (5G) wireless communication. The adopts gain-boosting technique that is comprehensively analyzed with transformer-based stacked-FET power amplifier (PA). Then, co-design of transmit/receive (T/R) switch PA low-noise (LNA) investigated, an electrostatic-discharge (ESD)-aware T/R incorporating...
This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods vertical gate (VG) Flash. A certain density may be achieved by any but with different numbers stacking layers. smaller pitch allows the achieving high at reasonable number stacked layers (≤ 32) thus potentially offers lower cost. VG has good scalability is very attractive. On other hand, it more difficult to decode bit line in architecture, innovations are required...
Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive 20nm 2D NAND. In this work, we propose a gate (VG) using self-aligned independently controlled double (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty cell size increase, making our VG as scalable conventional We present world's first <; 50nm...
The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward reverse diode operation modes are analyzed as a function device geometry, which strongly impact the corresponding failure mechanism. In mode, anode-to-cathode length reduction total width increase beneficial for robustness; however, in does not depend on saturates at around 400 V medium long lengths. mechanisms respectively attributed to current distribution Si substrate breakdown under...
In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel design with "initial-on" function is proposed achieve lowest trigger voltage and highest turn-on efficiency device effective on-chip ESD protection. Without using special native (NMOS almost zero or even negative threshold voltage) any process modification, this initial-on implemented by PMOS-triggered device, which can be realized in general processes. This has high enough holding avoid latchup...
Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, machine-model (MM) ESD robustness cannot achieve 150 V domains, although it can pass 2-kV human-body-model (HBM) test. The negative-to-VDD (ND) mode MM currents were discharged by circuitous current paths through to cause gate oxide damage, junction filament, and contact destruction internal transistors. detailed...
The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD n-channel metal-oxide-semiconductor (NMOS) was widely used to enhance robustness of a CMOS IC fabricated advanced processes. To further reduce occupied area RC circuit, new ESD-transient detection realized smaller capacitance has been proposed and verified 0.13-mum process. From experimental results, can achieve long-enough turn-on duration higher under...
FinFET technologies were seen as a potential roadblock for providing high ESD reliable ICs due to the 3D nature of narrow Si fins which do not allow large current conduction before thermal failure. However, detailed assessment common structures such diodes and grounded gate devices, has shown that reliability is finFET-based products. Studying both SOI bulk FinFETs, was found provide superior performance fin connection substrate. Focusing on sub-20-nm technologies, emerging challenges are...
MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor SCR device dominates trigger mechanism and current distribution govern voltage, holding on resistance, second breakdown current, ESD robustness device. should be optimized most advanced In addition, layout style can adjusted improve for protection.
Three system-level electrostatic discharge (ESD) design methodologies are compared using an RF buffer amplifier as case study. First, the ESD protection is designed with datasheet information. The obtained overdesigned optimized System-Efficient Design (SEED) methodology. SEED-based further human metal model testing and transient simulations. final requires five times less area on application board, capacitive loading six lower than when designing
The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup>...
A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination on-wafer characterization transient simulations enables ESD designer study behavior component-level protection during without adding off-chip devices. a solution can be long before IC packaging even final system built.
This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains a single perpendicular grain boundary (GB) in center recessed region were formed. can be attributed to lateral growth from un-melted solid seeds thick toward complete melting during ELC. Consequently, proposed RC-ELC TFTs possessing without GB channel exhibited...
The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of VG and its decoding method, we have developed several important innovations to optimize this technology: (1) "Shift-BL scramble" average BL capacitances, providing uniform C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL</sub> 's various memory layers; (2) Optimized read waveforms suppress hot-carrier induced disturb page reading...
A 28 GHz front-end module (FEM) for 5G communication is implemented in 22 nm FD-SOI technology. Competitive performance both TX and RX modes achieved simultaneously with robustness mode ESD protection. The key these features the transmit/receive (T/R) switch incorporating PA circuitry, offering high linearity mode, low NF ESD-protection capability. output stage uses a 3-stacked-FET topology to achieve power. Several matching techniques are equally distribute large voltage swing among three...
Gallium nitride (GaN) technologies have become an essential role in commercial advanced RF systems, which accompany emerging electrostatic discharge (ESD) reliability challenges. As opposed to ESD clamp transistors <i>LV</i> CMOS technologies, a mis-correlation between standard-defined human body model (HBM) robustness and commonly used TLP failure current was observed GaN (MIS) high electron mobility (HEMTs). Using transient HBM <inline-formula> <tex-math notation="LaTeX">${I}$...
The massively increasing data in computing world inspires the R&D of novel memory-centric architectures and devices. In this work, we propose a analog CIM technique for GEMM using 3D NOR Flash devices to support general-purpose matrix multiplication. Our analysis indicates that it's very robust use "billions" memory cells with modest 4-level large-spacing Icell produce good accuracy reliability, contrary past thinking pursue many levels each cell inevitably suffers loss. We estimate 2.7Gb...
NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired protection ability. All of them are based on a similar circuit scheme 3-stage inverters drive NMOS transistor large device dimension. In this work, designs 3-stage-inverter and 1-stage-inverter controlling studied verify optimal schemes in circuits.