A5008889108- Radio Frequency Integrated Circuit Design
- Microwave Engineering and Waveguides
- Advanced Power Amplifier Design
- Advancements in PLL and VCO Technologies
- Semiconductor materials and devices
- Photonic and Optical Devices
- Millimeter-Wave Propagation and Modeling
- Full-Duplex Wireless Communications
- VLSI and Analog Circuit Testing
- 3D IC and TSV technologies
- Electromagnetic Compatibility and Noise Suppression
- Telecommunications and Broadcasting Technologies
- Analog and Mixed-Signal Circuit Design
- Satellite Communication Systems
- IPv6, Mobility, Handover, Networks, Security
- GaN-based semiconductor devices and materials
- Advancements in Semiconductor Devices and Circuit Design
- Antenna Design and Analysis
- IoT and Edge/Fog Computing
- IoT Networks and Protocols
- Advanced Photonic Communication Systems
- VLSI and FPGA Design Techniques
- Advanced Manufacturing and Logistics Optimization
- Engineering and Materials Science Studies
IMEC
2013-2023
Vrije Universiteit Brussel
2012-2017
Delft University of Technology
2010
Millimeter-Wave transceivers with beamforming capabilities, such as the one presented in this work, are a key technology to reach 4 or 6Gb/s at 10m range IEEE 802.11ad standard. Moreover, for mm-Wave access 5G it will also be necessary boost peak data-rates far beyond 1Gb/s hundreds of meters small cells. Transceiver architectures often combine superheterodyne RF [1], leading high power consumption and suboptimal RX noise figure due losses circuitry. In contrast, 57-to-66GHz TRX IC paper,...
This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce new transformer-based combiner design method to achieve true-Doherty load modulation that uses compact footprint. The stages of the main PA auxiliary (aux. PA) both use differential...
A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path upconverted by I-Q mixers, while the amplitude modulates an RF-DAC. Aimed 802.11ad applications, 10 GS/s (i.e., 6x-oversampled) TX realizes more than 30 dB alias attenuation, input bandwidth exceeds 3.1 GHz. PA saturated output 10.8 dBm with 29.8% drain maximum RF-DAC code....
Obtaining sufficient EVM in all four 1.76GHz bandwidth chann1.76GHzels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels. Wireless applications often use digital low-power (LP) CMOS technology implement single-chip transceivers. The high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
An eight-way phased-array TRX front-end with RF phase shifting and on-chip transmit/receive switching is implemented in 28-nm CMOS. The TX P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dBout</sub> RX noise figure (NF) are 10 dBm 6.8 dB, respectively. active shifter shows less than 5° resolution amplitude errors within ± 0.35 dB. 9.6-mm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip consumes 231 mW 508 the mode from a 0.9-V...
This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 FD-SOI (fully-depleted on insulator), 130 SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes models together with de-embedding approaches are discussed described. Then, a general flow matching network (TMN) is introduced to...
This paper analyzes and demonstrates the use of coupled-LC tanks to enlarge locking range (LR) millimeter-wave (mm-wave) subharmonically injection-locked oscillators. Design guidelines are derived from a simplified analysis. Different techniques proposed tune tank. A mm-wave quadrature voltage-controlled oscillator in 40-nm CMOS verifies approach. The LR is larger than 2 GHz over 55-63-GHz tuning range. An on-chip envelope detector facilitates phase noise quadrature-phase imbalance uniform...
This paper presents a Doherty power amplifier (PA) in 22nm FD-SOI for achieving high output and backoff efficiency 28GHz 5G communications. The stage of the main PA auxiliary both use stacked-FET topology without posing reliability issue. A dedicated transformer-based matching network is proposed to achieve true load modulation while maintaining compact layout. fabricated technology with core area 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology the fifth generation (5G) wireless communication. The adopts gain-boosting technique that is comprehensively analyzed with transformer-based stacked-FET power amplifier (PA). Then, co-design of transmit/receive (T/R) switch PA low-noise (LNA) investigated, an electrostatic-discharge (ESD)-aware T/R incorporating...
Due to growing demand for higher data rates in wireless communication, high resolution requirement radars, and emerging sensing applications, mm-wave frequency bands have become very attractive recent years. Architectures circuits of transceivers are described comparison process technologies IC design is presented. Critical circuit blocks example implementations such as 60 GHz phased array, 28 front-end, 79 PMCW radar 145 FMCW discussed future trends identified.
This paper presents a 60 GHz TX/RX chipset in 40 nm CMOS technology flip-chip mounted on multilayer organic package with integrated phased-array antennas. The chips perform phase shifting of 4 antenna paths analog baseband. Short range (< 5 m) gigabit communication is proven by measurement wireless link between TX and RX modules.
A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. large locking range (10GHz), tunable over the 52-66GHz band, achieved using transformer-coupled resonators. simple calibration scheme proposed that only relies on relative power measurement of output signal. The wide range, tunability and make this design suitable for frequency synthesis communication systems.
A 60GHz polar Tx prototype implemented in 40nm CMOS includes a two-stage PA with an RF-DAC, I-Q upconversion mixer, LO hybrid and digital synchronization interface. Saturated output power is approx. 10dBm, while RF baseband input bandwidths are 9GHz 1.2GHz, respectively. The linear RF-DAC resolution 5 bits. EVM degradation spectral mask out-of-band distortion appear at powers higher than 6dB above P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A polar TX based on a 10GSample/s RF-DAC aimed at 802.11ad applications realizes more than 30dB alias attenuation and exceeds 3GHz input bandwidth with 6x oversampling factor. The PA drain efficiency is 29.8% P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 10.8dBm. Average output power 5.3dBm 15.3% running QPSK 3.3Gb/s datarate -23.6dB EVM. Corresponding 16-QAM values are: 3.6dBm 11.6% 6.7Gb/s -18.1dB 0.18mm <sup...
A 28 GHz front-end module (FEM) for 5G communication is implemented in 22 nm FD-SOI technology. Competitive performance both TX and RX modes achieved simultaneously with robustness mode ESD protection. The key these features the transmit/receive (T/R) switch incorporating PA circuitry, offering high linearity mode, low NF ESD-protection capability. output stage uses a 3-stacked-FET topology to achieve power. Several matching techniques are equally distribute large voltage swing among three...
An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB RX NF are 10dBm 6.8dB, respectively. active shifter shows less than 5° resolution amplitude errors within ±0.35dB. 9.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip consumes 231mW 508mW mode from a 0.9 V supply. When combined PCB antennas, ±46° scan angle obtained <0.4dB peak-to-peak gain ripples without...
We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) and maintain high power-added efficiency (PAE), differential 3-stacked transistors structure is used unit PA cell. The stability factor PAE are improved with capacitive neutralization shunt inductor intermediate node matching. Reliability issues under 2.4V...
A 28 nm CMOS 60 GHz polar transmitter (TX) is presented. It can handle modulations up to 64 QAM with a baud rate 1.76 Gbaud. Both amplitude and phase modulation are performed on chip at sample 5.28 GS/s. The saturated output power 12.6 dBm the peak drain efficiency 26.0 %. TX data of 10.56 Gb/s achieved DAC alias -19.4 dBc. With core area 0.115 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> this consumes 95.4 mW (without on-chip...
Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, circuit still has to follow the trend because a single chip integration offers key commercial advantages. To optimally achieve best performance/power/cost tradeoff with deeply scaled technology nodes, there clear paradigm shift towards intensive digitally assisted transceivers. Successes of such transceivers...
The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between -28.8 and -26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up 6.4 Gb/s. Its architecture, based on subharmonic injection locking, immune pulling by the power amplifier. A 24 phase-locked loop, designed low phase noise, locks quadrature oscillator. noise of resulting carrier -96.5 -93.8 dBc/Hz...
A complete Digital Front-End (DFE) processor for 60 GHz polar transmitter is presented. It avoids supply modulating, RF limiters, and AM detection circuits, compared to traditional analog-centric architectures. The front-end consists of i) a poly-phase Cascaded Integrator-Comb (CIC) filter spectrum shaping; ii) parallel Coordinate Rotation DIgital Computer (CORDICs) rectangular-to-polar conversion; iii) Power Amplifier (PA) non-linearities pre-distortion units using Look-Up Tables (LUTs)....
The availability of 9GHz bandwidth around 60GHz in combination with simple modulations schemes, low-cost radio ICs and small antenna size, allows for multi Gbit/s wireless communications. In this article the potential communications is evaluated from system, application user point view. Further, design challenges CMOS transceivers are identified. State-of-the-art designs show that short-range high-datarate links based on can be made, potentially helped beamforming.
A three-stage, transformer-coupled class-AB power amplifier (PA) and a super source-follower-based I-Q upconversion mixer are implemented in 40nm LP-CMOS technology. The transmitter (Tx) front-end is designed for multi-Gbps QPSK/QAM-16 signal transmission at 60GHz with improved back-off efficiency. It achieves 5.7% power-added efficiency (PAE) 5dB total consumption of only 90mW. Power gain output 1dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...