The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type are mostly limited to either one-antenna [1], or beamforming ICs that do not implement all radio functions [2]. sliding-IF architecture [3] uses RF phase shifting, which deteriorates noise performance.

Millimeter-Wave transceivers with beamforming capabilities, such as the one presented in this work, are a key technology to reach 4 or 6Gb/s at 10m range IEEE 802.11ad standard. Moreover, for mm-Wave access 5G it will also be necessary boost peak data-rates far beyond 1Gb/s hundreds of meters small cells. Transceiver architectures often combine superheterodyne RF [1], leading high power consumption and suboptimal RX noise figure due losses circuitry. In contrast, 57-to-66GHz TRX IC paper,...

This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce new transformer-based combiner design method to achieve true-Doherty load modulation that uses compact footprint. The stages of the main PA auxiliary (aux. PA) both use differential...

A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path upconverted by I-Q mixers, while the amplitude modulates an RF-DAC. Aimed 802.11ad applications, 10 GS/s (i.e., 6x-oversampled) TX realizes more than 30 dB alias attenuation, input bandwidth exceeds 3.1 GHz. PA saturated output 10.8 dBm with 29.8% drain maximum RF-DAC code....

This article analyses and demonstrates a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of automatic bandwidth control, effect gear-shift algorithm fast lock different noise contributions. The proposed scales up faster acquisition orderly reduces it jitter performance. contains digitally controlled...

This article presents novel methodologies and practical design considerations for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch...

This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO) in 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for phase noise reduction while maintaining low voltage swings reliability. In multi-core configuration, oscillators are coupled way that also simplifies LO distribution toward transmitter receiver. potential parasitic modes occur both configurations...

Obtaining sufficient EVM in all four 1.76GHz bandwidth chann1.76GHzels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels. Wireless applications often use digital low-power (LP) CMOS technology implement single-chip transceivers. The high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

An eight-way phased-array TRX front-end with RF phase shifting and on-chip transmit/receive switching is implemented in 28-nm CMOS. The TX P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dBout</sub> RX noise figure (NF) are 10 dBm 6.8 dB, respectively. active shifter shows less than 5° resolution amplitude errors within ± 0.35 dB. 9.6-mm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip consumes 231 mW 508 the mode from a 0.9-V...

Given the high throughput requirement for next generation wireless communication systems, merging millimeter wave technologies and multi-user MIMO seems a very promising strategy to achieve required 20 Gbps. Although full digital architecture provides best performance flexibility, its implementation at millimeter-wave frequencies today unrealistic due prohibitive costs power consumption. Hybrid analog-digital architectures, efficiently sharing beamforming operations between analog domains,...

This paper analyzes and demonstrates the use of coupled-LC tanks to enlarge locking range (LR) millimeter-wave (mm-wave) subharmonically injection-locked oscillators. Design guidelines are derived from a simplified analysis. Different techniques proposed tune tank. A mm-wave quadrature voltage-controlled oscillator in 40-nm CMOS verifies approach. The LR is larger than 2 GHz over 55-63-GHz tuning range. An on-chip envelope detector facilitates phase noise quadrature-phase imbalance uniform...

This paper presents a Doherty power amplifier (PA) in 22nm FD-SOI for achieving high output and backoff efficiency 28GHz 5G communications. The stage of the main PA auxiliary both use stacked-FET topology without posing reliability issue. A dedicated transformer-based matching network is proposed to achieve true load modulation while maintaining compact layout. fabricated technology with core area 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology the fifth generation (5G) wireless communication. The adopts gain-boosting technique that is comprehensively analyzed with transformer-based stacked-FET power amplifier (PA). Then, co-design of transmit/receive (T/R) switch PA low-noise (LNA) investigated, an electrostatic-discharge (ESD)-aware T/R incorporating...

This paper presents a D-band front-end module (FEM) with an integrated transmit/receive (T/R) switch in 22-nm fully-depleted silicon on insulator (FD-SOI) CMOS technology for beyond-5G communication. The asymmetric T/R topology intrinsic ESD protection leverages the Tx- and Rx-mode RF performance. Both PA LNA have differential transformer-based matching networks to eliminate unwanted effects from common-mode parasitics, especially at antenna port. adopted stacked-FET achieves high output...

This paper presents a K/Ka-band voltage biased differential LC-VCO in 22nm FD-SOI achieving 1/f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> corner below 18 kHz and figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to flicker noise filtering technique, upconversion can be suppressed significantly without degrading phase (PN) xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> region. The...

Due to growing demand for higher data rates in wireless communication, high resolution requirement radars, and emerging sensing applications, mm-wave frequency bands have become very attractive recent years. Architectures circuits of transceivers are described comparison process technologies IC design is presented. Critical circuit blocks example implementations such as 60 GHz phased array, 28 front-end, 79 PMCW radar 145 FMCW discussed future trends identified.

This paper presents a 60 GHz TX/RX chipset in 40 nm CMOS technology flip-chip mounted on multilayer organic package with integrated phased-array antennas. The chips perform phase shifting of 4 antenna paths analog baseband. Short range (< 5 m) gigabit communication is proven by measurement wireless link between TX and RX modules.

A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. large locking range (10GHz), tunable over the 52-66GHz band, achieved using transformer-coupled resonators. simple calibration scheme proposed that only relies on relative power measurement of output signal. The wide range, tunability and make this design suitable for frequency synthesis communication systems.

This paper presents a 40nm CMOS transformer-based dual-band VCO with differential hybrid coupler for I/Q generation. The average phase noise of the combination over 54 to 69.3GHz tuning range is −90dBc/Hz at 1MHz offset while best FOM value 177dB. Along wide from 67GHz, mismatch less than 3°. area only 60μm∗65μm.

A 28 GHz front-end module (FEM) for 5G communication is implemented in 22 nm FD-SOI technology. Competitive performance both TX and RX modes achieved simultaneously with robustness mode ESD protection. The key these features the transmit/receive (T/R) switch incorporating PA circuitry, offering high linearity mode, low NF ESD-protection capability. output stage uses a 3-stacked-FET topology to achieve power. Several matching techniques are equally distribute large voltage swing among three...

An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB RX NF are 10dBm 6.8dB, respectively. active shifter shows less than 5° resolution amplitude errors within ±0.35dB. 9.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip consumes 231mW 508mW mode from a 0.9 V supply. When combined PCB antennas, ±46° scan angle obtained <0.4dB peak-to-peak gain ripples without...

We present a 22.5-27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of proposed gear-shift algorithm, scaling up PLL bandwidth faster settling, and orderly reducing it jitter performance. A digitally controlled oscillator (DCO), based on transformer feedback tunable source-bridged capacitor, exhibits low phase noise (PN) over wide tuning range (FoM -184 dBc/Hz FoMT -191 dBc/Hz). occupies 0.09-mm2...

We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) and maintain high power-added efficiency (PAE), differential 3-stacked transistors structure is used unit PA cell. The stability factor PAE are improved with capacitive neutralization shunt inductor intermediate node matching. Reliability issues under 2.4V...

We present a 60 GHz four-antenna phased-array direct conversion receiver in 90 nm RF CMOS with an LO based on subharmonic injection locking, beamforming that is partially the path and at analog baseband, baseband section. The system features set of four oscillators, locked to fifth harmonic central oscillator, improving phase noise performance robustness. Phase shifting realized two steps domains, which reduces complexity shifters signal degradation baseband. Signal combination performed...