A5035170564- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies
- 3D IC and TSV technologies
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Electrostatic Discharge in Electronics
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
Pohang University of Science and Technology
2022-2024
Samsung (South Korea)
1997-2010
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture proposed decreases standby and active power by 50 25%, respectively. It also increases I/O speed to <formula formulatype="inline"><tex Notation="TeX">${>}\,$</tex> </formula>1600 Mb/s for 4 rank/module 2 module/channel case since master isolates all...
This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using 500-MHz clock generator and full CMOS rail-to-rail power swing. consumed by the circuit measured to be 28 mW/pin, when connected 10-pF load, at 1.8-V supply voltage. transmitter uses push-pull linear output driver automatic impedance controller, achieving reduction currents voltage margin as large 200 mV. receiver employs hierarchical sampling...
Accurate current-voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</i> ) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, current BSIM does not support a buried-channel-array (BCAT), which structure of state-of-the-art commercial dynamic random access memory (DRAM) cell transistor. In this work, we propose an intelligent...
A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics charge pump, is proposed. It makes output pump virtually grounded, eliminate current mismatch and seamlessly convert locking information into digital form. DLL designed fabricated exhibit duty-cycle corrector performance with a speed 1.4 Gb/s.
This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the voltage difference (/spl Delta/V/sub BL/) as well GS/ margin by boosting node with dependent capacitor and 2) an I/O current sense amplifier high gain using cross-coupled mirror control reduced temperature sensitivity simple temperature-compensation scheme. An experimental 16 Mb DRAM chip 0.18-/spl mu/m twin-well, triple-metal CMOS...
A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use 500MHz clock generator and full CMOS power rail swing. This fabricated on 0.10/spl mu/m process in 330x66/spl mu/m/sup 2/. The transceiver 200mVx690ps passing eye-windows channel over 1.8V supply.
A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the scheme accomplishes both goals, discharging capability C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> (input capacitance) reduction. The fabricated chips with new passed severe package level EOS test conditions such HBM-5 kV MM-500 V stress....
This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers constant to ring oscillator over wide range of voltage. Thereby, the dynamic voltage droop due variations in workload is compensated while margin mass production improved. Since SNC technique operates independently loop bandwidth without using...
The degradation of the fin-type buried-channel-array transistor (BCAT) in dynamic random access memory (DRAM) cell is investigated under Fowler–Nordheim stress at various temperatures, including 77 K. While increase OFF current dominated by Shockley–Read–Hall junction leakage, threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> )...