Jian Li

ORCID: 0000-0002-5239-9469
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About
Contact & Profiles
Research Areas
  • Cloud Computing and Resource Management
  • Parallel Computing and Optimization Techniques
  • Aluminum Alloys Composites Properties
  • Advanced materials and composites
  • Metal and Thin Film Mechanics
  • Advanced Data Storage Technologies
  • X-ray Diffraction in Crystallography
  • Crystallization and Solubility Studies
  • Advanced ceramic materials synthesis
  • Embedded Systems Design Techniques
  • Software-Defined Networks and 5G
  • Interconnection Networks and Systems
  • Corrosion Behavior and Inhibition
  • Distributed and Parallel Computing Systems
  • IoT and Edge/Fog Computing
  • Metallurgy and Material Forming
  • Metal Alloys Wear and Properties
  • Synthesis and properties of polymers
  • COVID-19 and healthcare impacts
  • Astrophysics and Cosmic Phenomena
  • Hydrogen embrittlement and corrosion behaviors in metals
  • MXene and MAX Phase Materials
  • Bone Tissue Engineering Materials
  • Boron and Carbon Nanomaterials Research
  • Powder Metallurgy Techniques and Materials

Fudan University
2013-2025

Gansu Agricultural University
2024-2025

University of Science and Technology of China
2024-2025

First Affiliated Hospital of GuangXi Medical University
2024-2025

Guangxi Medical University
2024-2025

Nanjing University
2024-2025

University of California, Los Angeles
2022-2025

Tsinghua University
2004-2025

Academy of Military Medical Sciences
2024-2025

Xidian University
2024

Caching techniques have been an efficient mechanism for mitigating the effects of processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially in context chip multiprocessors (CMPs), present many challenges area requirements, core-to-cache balance, power consumption, and design complexity. New advancements technology enable caches to be built from other technologies, such as Embedded DRAM (EDRAM), Magnetic RAM (MRAM), Phase-change (PRAM), both 2D chips or 3D...

10.1145/1555754.1555761 article EN 2009-06-20

Deep learning inference on embedded devices is a burgeoning field with myriad applications because tiny are omnipresent. But we must overcome major challenges before can benefit from this opportunity. Embedded processors severely resource constrained. Their nearest mobile counterparts exhibit at least 100 -- 1,000x difference in compute capability, memory availability, and power consumption. As result, the machine-learning (ML) models associated ML framework not only execute efficiently but...

10.48550/arxiv.2010.08678 preprint EN other-oa arXiv (Cornell University) 2020-01-01

Tumor-associated macrophages have emerged as crucial factors for metastases. Microglia are indispensable components of the brain microenvironment and play vital roles in metastasis (BM). However, underlying mechanism how activated microglia promote non-small cell lung cancer (NSCLC) remains elusive. Here, we purified lines with brain-metastatic tropism employed a co-culture system to reveal their communication microglia. By single-cell RNA-sequencing transcriptome difference analysis,...

10.1038/s41392-022-00872-9 article EN cc-by Signal Transduction and Targeted Therapy 2022-02-23

Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus multiprogrammed workloads. Nonetheless, parallel computation of a single application is critical in light the expanding performance demands important future This work addresses problem dynamically optimizing power consumption that executes many-core CMP under given constraint. The optimization space two-dimensional, allowing changes number active processors and applying dynamic...

10.1109/hpca.2006.1598114 article EN 2006-03-21

Energy consumption has become a major concern to the widespread deployment of cloud data centers. The growing importance for parallel applications in introduces significant challenges reducing power drawn by hosted servers. In this paper, we propose an enhanced energy-efficient scheduling (EES) algorithm reduce energy while meeting performance-based service level agreement (SLA). Since slacking non-critical jobs can achieve saving, exploit slack room and allocate them global manner our...

10.1109/ccgrid.2012.49 article EN 2012-05-01

Topical minoxidil, approved by the FDA in 1980s, has been widely used to manage androgenetic alopecia. While effective, several adverse events (AEs) related its use, especially those not well-documented on product labels, remain a concern. This study aimed evaluate safety of topical minoxidil analyzing AEs reported Adverse Event Reporting System (FAERS) from 2004 2024, focusing identifying potential risk signals highlighted current labels. event reports(AERs) FAERS, where was identified as...

10.1080/14740338.2025.2467816 article EN Expert Opinion on Drug Safety 2025-02-13

Much research has been devoted to making microprocessors energy-efficient. However, little attention paid multiprocessor environments where, due the cooperative nature of computation, most energy-efficient execution in each processor may not translate into overall execution. We present thrifty barrier, a hardware-software approach saving energy parallel applications that exhibit barrier synchronization imbalance. Threads arrive early pick among existing low-power sleep states based on...

10.1109/hpca.2004.10018 article EN 2005-03-31

Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change (PRAM), offer dramatically different power-performance characteristics when compared with SRAM-based caches, particularly in the areas static/dynamic power consumption, read write access latency cell density. In this paper, we propose to take advantage best that each technology has through use read-write aware Hybrid Cache Architecture (RWHCA) designs, where a single level cache can be partitioned...

10.5555/1874620.1874803 article EN Design, Automation, and Test in Europe 2009-04-20

Caching techniques have been an efficient mechanism for mitigating the effects of processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially in context chip multiprocessors (CMPs), present many challenges area requirements, core-to-cache balance, power consumption, and design complexity. New advancements technology enable caches to be built from other technologies, such as Embedded DRAM (EDRAM), Magnetic RAM (MRAM), Phase-change (PRAM), both 2D chips or 3D...

10.1145/1555815.1555761 article EN ACM SIGARCH Computer Architecture News 2009-06-15

In recent years large graph processing has emerged to be a popular application for companies because of the increasing Web and social networks. The ever growing scale graphs emergence cloud computing poses challenges their efficient cost-conscious scheduling approach tasks. this paper, we focus on use resources dispatching We design novel framework EComer that can easily integrated into existing infrastructure. key component is heuristic, called CCSH, which an extension Heterogeneous...

10.1109/hpcc.2011.147 article EN 2011-09-01

10.1016/j.ijhydene.2016.08.213 article EN publisher-specific-oa International Journal of Hydrogen Energy 2016-10-28
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