A5042433136- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Electrostatic Discharge in Electronics
- Physical Unclonable Functions (PUFs) and Hardware Security
Boeing (United States)
2019-2021
Behavioral Tech Research, Inc.
2021
Vanderbilt University
2013-2019
D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to heavy-ion tested tilt angle 55°, and one order cross-section 75° less 50% area penalty compared unhardened designs.
Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and transient (SET) pulse widths shrink to on order setup-and-hold time flip-flops, probability latching an SET as SEU must be reevaluated. In this paper, previous assumptions about relationship pulsewidth are reconsidered a model has been developed advanced technologies. A method using improved data used predict section. The...
Angular single-event (SE) mechanisms and experimental upset data for 14-/16-nm bulk fin field-effect transistor (FinFET) technologies are presented analyzed. The discrete structure of FinFETs introduces unique geometrical orientation dependences angular SE (SEU) responses FinFET circuits. Geometric analyses 3-D technology computer-aided design results effectively explain the behind experimentally observed cross-sectional responses. Results show that SEU characteristics can be attributed to...
Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 silicon-on-insulator (SOI). The effects threshold voltage body contact are shown to significantly impact SET response advanced SOI technologies. Also, reverse cumulative distribution is extracted count for several targets be a useful aid selecting temporal filtering radiation-hardened circuitry.
Two 32nm SOI single-event upset test chips have been irradiated at LBNL and TAMU heavy ion facilities. The include unhardened RHBD designs such as DICE, LEAP stacking devices. SEU cross-section data are presented for the hardened flip-flop across facility, beam tune, angle of incidence, clock frequency.
Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI responses, which has commonly been observed. Data show than 30× in SE upset (SEU) LET threshold 3 orders of magnitude decrease saturated cross section FinFETs when compared to FinFETs. The SEU is shown be due saturation transient (SET) pulsewidths at values that are feedback-loop delays DFF design technology....
A new geometry-aware single-event enabled compact model for sub-50 nm partially depleted silicon-on-insulator MOSFETs is presented. The extends the bias-dependent modeling methods with an integrated parasitic BJT using SPICE Gummel Poon equations and parameters derived from manufacturer's process design kit, physical layout, technology information. compares well TCAD test data.
Single-event transient (SET) data for the 14-/16-nm bulk finFET technology generation are presented and analyzed variations in threshold voltage number of fins transistor. The heavy-ion experimental over a range supply allows comparison impact drive current on SET response each transistor variant. results show that is key factor determining pulsewidths cross sections high linear energy transfer particle irradiation. Transistor variant result matching an excellent match sections.
Single-event transients (SETs) in 16-/14-nm bulk fin field effect transistor (finFET) logic chains have been measured using a custom-designed test IC. A variety of gate were designed, and SET pulse widths obtained across wide range supply voltages. In light the increased response at reduced voltages, efficacy filter-based mitigation is assessed by analyzing voltage dependence duration against characteristic electrical inverter delay.
Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement over 300 000 SETs across 12 combinational logic variants 415 SEUs three D-flip-flop designs large test matrix heavy-ion linear energy transfer, angle incidence, supply voltage only 319 runs with total time 108 h. A similar-sized data set equivalent coverage, using traditional serial testing...
A combinational logic family, termed dual-interlocked (DIL), designed for single-event transient (SET) mitigation has been fabricated at a 16nm/14nm bulk FinFET technology generation and irradiated with heavy ions. Through both simulation heavy-ion irradiation, DIL is shown to be robust single- dual-node strikes. Results are compared cascode voltage switch standard show the effectiveness of family in mitigating SETs gate level. Three exemplar radiation-hardened-by-design synchronous systems...
A comprehensive data set of heavy-ion induced single-event transients has been collected for inverter chains fabricated in the IBM 32nm partially-depleted silicon-on-insulator technology across various bias voltages, transistor variants, ion energies and angles incidence.
A single-event-enabled compact model for bulk FinFET technologies has been developed and integrated with a process design kit (PDK) an industry standard electronic automation tool flow. The incorporates transistor bias dependence 3-D ion-incidence geometry awareness into the calculation of single-event-generated current waveform. performance from nominal supply circuit operation down to near-threshold voltage applications. technology computer-aided simulations have used calibrate transient...
We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the compared to previous partially technology generations (32 45 nm). per-bit cross section is approximately an order of magnitude lower than higher onset linear energy transfer (LET). No dependence roll angle or input pattern was found. Tilt data follow cosine law. Increasing...
At the 14-/16-nm FinFET technology node, experimental heavy-ion single-event upset (SEU) cross sections have been obtained for a D flip-flop (DFF) with variation in supply voltage over wide range of particle linear energy transfer (LET). An empirical model predicting SEU section as function based on data has developed and verified. The results are consistent low-LET irradiation findings from previous works that indicated strong exponential increase scaling technologies. Furthermore, this...
Heavy-ion irradiations of 14/16-nm node bulk FinFET combinational logic circuits under different supply voltage and frequency are investigated. Results indicate that particle LET strongly affects soft-error rate (SER). Single-event transient (SET) experimental data models for SER used to explain the differences in low-LET particles high-LET particles.
A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast capable causing an error. has been developed overcome this using latch as feedback-assisted circuit. Single-event upset (SEU) data are combined with SET extend pulsewidth acuity such that pulses faster than the extracted. The...