In this paper, a linear CMOS power amplifier (PA) with high output (34-dBm saturated power) for data-rate mobile applications is introduced. The PA incorporates parallel combination of four differential cores to generate good efficiency and linearity. To implement an efficient on-chip combiner in small form-factor, we propose parallel-series combining transformer (PSCT), which mitigates drawbacks limitations conventional power-combining transformers such as series (SCT) (PCT). Using the...

In practice, including large number of assets in mean-variance portfolios can lead to higher transaction costs and management fees. To address this, one common approach is select a smaller subset from the larger pool, constructing more efficient portfolios. As solution, we propose new asset selection heuristic which generates pre-defined list candidates using surrogate formulation re-optimizes cardinality-constrained tangent portfolio with these selected assets. This method enables faster...

A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-μm CMOS technology. For the average efficiency enhancement, operation realizes a switched-quadrature coupler with topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize isolation port of as signal path low-power (LP) mode operation, incorporated output matching network satisfies |Γ| = 1 condition from quadrature LP while providing necessary load-pull impedance side...

This paper proposes a new vector-sum type variable-phase shifter (VPS) topology for predistorting the phase of modulated signal an analog-predistortion power amplifier system. It has continuous linear-in-degree control curve over 90° phase-control range and smallest size among all those proposed CMOS works. The utilizes improved RC poly-phase filter to generate in-phase quadrature-phase vectors. uses fewer components but wider phase-splitting bandwidth than traditional filters, reducing loss...

To predistort the signal of an analog-predistortion power amplifier system, this paper proposes a variable gain (VGA) topology that gives optimized linearity and bandwidth performance while having continuous, linear-in-decibel control curve. The design employs self-biased differential with dynamic current source to provide linearity. overall VGA is then controlled by highly linear attenuator connected at output amplifier. This separated controlling stage allows have continuous curve without...

A novel feedback bias technique for a multistage cascode topology is developed to improve the linearity and reliability of power amplifiers (PAs). Due large parasitic capacitance low substrate resistivity CMOS technology, signal swings are coupled between ports transistors. The proposed method utilized RF leakage signals at gate common-gate (CG) transistor in employing negative feedback, which not only enhances PA, but also alleviates voltage stress drain CG device from 4.5 1.9 V. This...

A 6-bit digital phase shifter in 0.18-μm silicon-oninsulator (SOI) process is presented. It operates over a 4-7-GHz frequency band and provides 360° of coverage with 5.625° resolution using 64 states. The SOI has compact size 1320 μm × 780 μm. Compared to state-of-the-art 0.15-μm pHEMT-based product design, the IC design five times smaller 2-6 dB higher IP3 power handling capability. To best authors' knowledge, this highest commercial technology. These monolithic microwave integrated circuit...

The 5-GHz quadrature couplers implemented in GaAs and silicon-based integrated passive device (IPD) technologies are presented. Although technology is superior to terms of substrate resistivity back-side vias, the coupler using a silicon IPD process achieved better insertion loss due thick metal traces comparable resistivity. While employed 4-μm-thick traces, 10.8-μm-thick realized with via connections between top 5.3-μm thickness bottom 5.5-μm thickness. showed 0.15 0.27 dB loss,...

A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices driver stage and in cascode configurations by a network enhancing linearity. To achieve high efficiency linearity simultaneously, large-signal IMD minimum (IMD sweet spot) properly used at desired output level. proposed PA was fabricated 0.18-μm technology. experimental results demonstrate gain 26 dB, maximum dBm...

We report on room temperature electroluminescence (EL) from n–n isotype heterostructures composed of Al-doped graded-band-gap Zn 1− x Mg O (g-ZnMgO : Al) and ZnO films fabricated Pt/Ti/SiO 2 /Si substrates. The heterostructure device generated EL emission at operation voltages as low 3–5 V, whose spectra covered visible near infrared regions under the unipolar condition, with g-ZnMgO Al positive. intensity light increased nonlinearly short-wavelength emissions in region became appreciable...

ABSTRACT This article presents the design and implementation of a high‐performance, compact spiral‐coupled directional coupler using an advanced integrated passive device (IPD) fabrication process on GaAs substrate for use in mobile radio frequency identification (RFID) reader applications. The IPD step is introduced specifically to enable coupler, which constructed by transformation intertwined mutual inductors air‐bridges, have size high Q‐factor. fabricated achieves only 0.43 dB insertion...

A compact quadrature coupler — using intertwined mutual inductors by the proposed GaAs integrated passive device (IPD) process is developed considering quality factor of inductor and minimum insertion loss for long term evolution (LTE) applications. At center frequency LTE bands 5 8, achieved −3.45dB S21 −3.43dB coupling S41 with less than 0.65 degrees phase error over range. The reflection coefficient S11 isolation S31 are −24.32dB −23.45dB, respectively. This can be usable a 3-dB...

A 1.95 GHz linear power amplifier (PA) in a standard 0.18 µm CMOS process is presented. The PA achieves the load insensitivity characteristic up to 2.5:1 VSWR condition and dual-mode operation with balanced topology. area of 1.6 × 1 mm2. With 3.4 V supply, provides 40.4% peak power-added efficiency (PAE) 35% PAE at 26.4 dBm output power.

Nanosize Si-tip arrays with gated electrodes have been fabricated using the self-aligned method. In order to a parallel electron beam (high perveance beam) toward anode plate, we designed nanosize tip array heights of slightly less than that gate electrode. A high is supposed provide better focusing beams. Hence, it important for nanolithographic application. The procedures nanoscale are reactive ion etching, sharpening, and oxidation followed by 7:1 BHF oxide etch. metal fabrication...

A new linearity improvement technique is introduced for a class-AB CMOS Power Amplifier (PA). The proposed PA has two stages and each stage cascode configuration. direct feedback path from the input of power to driver via an Accumulation-mode MOS (AMOS) varactor adopted improve linearity. This additional provides negative loop second-order harmonic, AMOS controls gain amount phase shift signals. been implemented in standard 0.18-μm technology. measured results show 21.4 dB, maximum output...

A linear voltage controlled variable resistor in partially depleted silicon-on-insulator (PD-SOI) technology is presented. Stacked FET structure utilized for the implementation and control of gate body provides wide resistance tuning range. Also, use stacked varistor demonstrated improved IP3 P1dB linearity. This can be applicable to tunable load impedance, series parallel feedback attenuation, as a part system or discrete component.

A 45nm SOI-CMOS PLL with a wideband LC-VCO is presented. The proposed uses the advantage of SOI technology such as small parasitic capacitance and high Q-factor. frequency range maximized because maximum-to-minimum ratio capacitor bank. Measurement results show that VCO generates 4.87-to-9.65GHz signals 65.8% coverage. Fabricated chip occupies 0.09mm2 active area consumes less than 7mA current from single 1.0V supply.

Summary form only given. Nanosize Si-tip arrays with gated electrodes have been fabricated using self-aligned method. In order to parallel electron beam (high perveance beam) toward the anode plate, we designed a nanosize tip array heights of slightly less than that gate electrode. High is supposed provide better focusing beams. Hence, it important high for nano lithographic application.

The pragmatically coded 2D AM using multilevel coding technique is presented for the channel scheme of HDTV transmission environment. proposed has a asymptotically equal performance to original pragmatic code and requires less computational load.