<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high PA design, two types of transformers, series-combining and parallel-combining, fully analyzed compared in detail to show parasitic resistance turn ratio as limiting factor combining. Based on analysis, kinds parallel-combining a two-primary 1:2 three-primary ratio, incorporated into...

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum process is presented. Using parallel-combining transformer (PCT) and gate bias adaptation, discrete control of the PA achieved for enhancing efficiency at back-off. With 3.3 V supply, has peak drain 33% 31 dBm output power. By applying control, reduction 650 mA current consumption can be over low range while satisfying EVM requirements WLAN 802.11g WiMAX 802.16e signals.

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. switched capacitor fully analyzed to implement a in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, 3.3-V 2.4-GHz PA implemented 0.18-μm process. The has two modes, high-power low-power (LP), each mode optimally matched by network. LP enables more than 50% dc current reduction from 0- 10-dBm range. improved efficiency this...

A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a loss due the slow transition of common-gate device from triode region cut-off region. To minimize PAs, we propose charging acceleration technique, CAT. This method incorporates capacitive element between drain and source configuration, accelerating speed responsible for turning off instantly after common-source is turned thus minimizing...

A CMOS millimeter-wave (mmWave) downconversion mixer with a local-oscillator (LO) buffer is proposed for wireless Gb/s data-transfer enabling systems, such as 5G systems. To obtain high linearity at low supply voltages, the mmWave adopts an on-chip transformer-based topology. In order to achieve differential single-ended conversion and IF output matching, while maintaining performance, incorporates active balun common-source common-drain configurations employing common-mode noise third-order...

In this letter, a multi-level and multi-band Class-D CMOS power amplifier (PA) in standard 0.18 ¿m process is presented. Using multiple PMOS devices with control switches, the proposed PA improves efficiency operation. order to enable operation, employs tunable series resonator. The measured maximum drain efficiencies were 72% 70% for low mode high mode, respectively. 3 dB bandwidth of system was from 450 MHz 730 MHz, which covers cognitive radio white spectrum standard. EVM using commercial...

A novel feedback bias technique for a multistage cascode topology is developed to improve the linearity and reliability of power amplifiers (PAs). Due large parasitic capacitance low substrate resistivity CMOS technology, signal swings are coupled between ports transistors. The proposed method utilized RF leakage signals at gate common-gate (CG) transistor in employing negative feedback, which not only enhances PA, but also alleviates voltage stress drain CG device from 4.5 1.9 V. This...

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It based on the analysis of operation and loss mechanism class-E PAs, which includes effects a finite dc-feed inductance an impedance matching transformer. Using proposed approach, PA with 2 <formula formulatype="inline"><tex Notation="TeX">$\times$</tex> </formula> 1:2 step-up on-chip transformer was...

An external capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using loop-gain stabilizer (LGS) fix dc level output voltage error amplifier optimal value, LDO keep maximizing unity-gain frequency, while changes widely up 200 mA. Despite multiple poles in regulating loop, stability easily be obtained due an intrinsic left-half plane zero, generated by auxiliary path LGS. The...

This brief presents a nonisolated multilevel linear amplifier with nonlinear component (LINC) power (PA) implemented in standard 0.18-μm complementary metal-oxide- semiconductor process. Using combiner, the overall efficiency is increased by reducing wasted at combined out-phased signal; however, low still needs to be improved. To further improve of low-power (LP) mode, we propose multiple-output power-level LINC PA, load modulation switches. In addition, analysis proposed design on system...

In this letter, we present a linear InGaP/GaAs HBT power amplifier (PA) with parallel-combined transistors for small-cell applications. Ballast resistors bypass and capacitors are employed in transistors. When the set to appropriate values, IMD3 components of found be out phase each other by 180° canceled at output. The experimental results show that proposed PA produces saturated output 33.5 dBm 0.88 GHz, power-added efficiency (PAE) 46.1% 5-V supply voltage. To validate effectiveness...

In this paper, a novel monolithic voltage-boosting parallel-primary transformer is presented for the fully integrated CMOS power amplifier design. Multiple primary loops are interweaved in parallel to combine AC currents from multiple devices while higher turn ratio of secondary loop boosts voltages combined at load loop. The proposed structure much more compact and separable devices, avoiding potential instability. To verify feasibility combining method, switching was implemented standard...

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology used the VCO, generates pair of 30GHz differential outputs and single-ended 60GHz output. The are followed by proposed divider. divider incorporates active loads peaking to achieve higher bandwidth. maximum operating was found be much than f/sub T//2 transistor. To best...

The linear amplifier with nonlinear components (LINC) is highly efficient because it uses a power (PA). However, the linearity performance of LINC system easily degraded by amplitude and phase mismatches between two paths. In this paper, we propose novel mismatch calibration technique for that calibrates both only control. detects paths without any iteration using predefined five test vector signals. addition, corrects path unbalanced Therefore, proposed scheme does not require additional...

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology WLAN CMOS PAs is proposed obtain broadband with compact using the wafer-level package technology. To achieve highly linear output high efficiency across 1-GHz bandwidth 5G-band PA, reconfigurable interstage matching transformer are proposed. For...

This paper newly presents a push-pull parallel-combined CMOS power amplifier (PA) and its analysis of operation. The proposed class-E PA incorporates the devices with 1:1:2 (two single-turn primary windings two-turn secondary winding) step-up on-chip transformer. is fully integrated in standard 0.18- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m technology without any external balun or matching networks. operation multi-turn transformer...

A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices driver stage and in cascode configurations by a network enhancing linearity. To achieve high efficiency linearity simultaneously, large-signal IMD minimum (IMD sweet spot) properly used at desired output level. proposed PA was fabricated 0.18-μm technology. experimental results demonstrate gain 26 dB, maximum dBm...

This paper presents a linear CMOS power amplifier (PA) for mm-wave 5G applications. A compact 8-way parallel-parallel combiner is proposed to increase Pout with low loss and symmetrical phase/amplitude. The IMD3 cancellation method presented in this work obtain high P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> PAE. PA 65-nm shows 23.2dBm 33.5% PAE CW signals at 28GHz. It achieves the highest of 17.6% an average 18.02dBm -31.2dB...

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated standard 40-nm CMOS process. In comparison transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, does so compact die area. With 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, PA achieves 19.7 15.7 dBm average output powers PAEs 17.1% 13%, HP LP respectively, while...

We present a 1.9-GHz high-power-handling complementary metal-oxide-semiconductor (CMOS) transmit/ receive (T/R) switch with the impedance transformation technique (ITT). The losses of T/R switch, including matching networks, are analyzed, and design method for selection an optimal operating (RSW) is presented. proposed implemented in standard 0.18-μm CMOS process. Experimental data show that achieves more than 2 W power-handling capability.

In this paper, a fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11g WLAN applications with the proposed combining transformer. comparison conventional transformers, transformer can offer performances smaller die size. The fabricated two-stage PA using 65nm technology achieves saturated output of 26.7 dBm drain efficiency (DE) 47.7% at 2.48 GHz. tested 54Mbps signal and it meets stringent error vector magnitude (EVM) spectral mask requirements 20.13-dBm...

A high-power single-pole-double-throw (SPDT) antenna switch using a differential architecture and multi-section impedance transformation technique is demonstrated in standard 0.18-μm CMOS process. The prevents unwanted channel formation of OFF-state Rx transistors by relieving the voltage swing over devices. In addition to this architecture, helps reduce even more, contributing significant enhancement power handling capability. loss whole design block including matching networks has been...

This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel-combined transistors and selective adaptive biasing. An bias circuit is applied to one of the take advantage both transistor method biasing at target output region. By using proposed biasing, can be maximized, resulting in higher added efficiency (PAE). The experimental results show that PA has saturated 26.9 dBm 2.48 GHz PAE 40.3% 3.3-V supply voltage. also tested modulation coding...

Design equations for the parameters of a lumped-element quadrature coupler with impedance transforming are derived. Considering on-chip implementations, it has smaller size as compared to quarter-wavelength transmission-line-based coupler. A 2.47-GHz is implemented using GaAs technology verification. The measurement results show that fabricated achieves an insertion loss 3.39 dB phase imbalance 0.8° through and coupled outputs at 2.47 GHz.

A 24-GHz direct-conversion transmitter is proposed for in-cabin radar applications. The RF consists of an I/Q up-conversion mixer, local (LO) oscillator generator, and a power amplifier. To improve the linearity inverter transconductor with third-order intermodulation (IM3) distortion cancellation proposed. balancing performance LO poly-phase filter, including parasitic line inductance, By employing highly linear mixer balanced achieves high characteristics. It fabricated in 65-nm CMOS...