A5101027920- Cryptographic Implementations and Security
- Radio Frequency Integrated Circuit Design
- Advanced Power Amplifier Design
- Chaos-based Image/Signal Encryption
- Coding theory and cryptography
- Quantum Computing Algorithms and Architecture
- Quantum-Dot Cellular Automata
- Full-Duplex Wireless Communications
- Microwave Engineering and Waveguides
- Advanced Malware Detection Techniques
- Physical Unclonable Functions (PUFs) and Hardware Security
- GaN-based semiconductor devices and materials
- Digital and Cyber Forensics
- Low-power high-performance VLSI design
- Privacy, Security, and Data Protection
- Embedded Systems Design Techniques
- Quantum Information and Cryptography
- VLSI and Analog Circuit Testing
- Internet of Things and Social Network Interactions
- Electromagnetic Compatibility and Noise Suppression
Kookmin University
2022-2024
Pusan National University
2016-2018
In this letter, we present a linear InGaP/GaAs HBT power amplifier (PA) with parallel-combined transistors for small-cell applications. Ballast resistors bypass and capacitors are employed in transistors. When the set to appropriate values, IMD3 components of found be out phase each other by 180° canceled at output. The experimental results show that proposed PA produces saturated output 33.5 dBm 0.88 GHz, power-added efficiency (PAE) 46.1% 5-V supply voltage. To validate effectiveness...
This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated standard 40-nm CMOS process. In comparison transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, does so compact die area. With 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, PA achieves 19.7 15.7 dBm average output powers PAEs 17.1% 13%, HP LP respectively, while...
In this paper, a fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11g WLAN applications with the proposed combining transformer. comparison conventional transformers, transformer can offer performances smaller die size. The fabricated two-stage PA using 65nm technology achieves saturated output of 26.7 dBm drain efficiency (DE) 47.7% at 2.48 GHz. tested 54Mbps signal and it meets stringent error vector magnitude (EVM) spectral mask requirements 20.13-dBm...
This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel-combined transistors and selective adaptive biasing. An bias circuit is applied to one of the take advantage both transistor method biasing at target output region. By using proposed biasing, can be maximized, resulting in higher added efficiency (PAE). The experimental results show that PA has saturated 26.9 dBm 2.48 GHz PAE 40.3% 3.3-V supply voltage. also tested modulation coding...
A parallel-segmented primary autotransformer is proposed to optimize passive efficiency as well impedance transformation ratio. In addition, a corresponding equivalent lumped model has been and shows good agreement with electromagnetic -simulated measured data. This paper also presents fully integrated HBT power amplifier obtain watt-level output low loss. The saturated of the (PA) 31 dBm at 2.3 GHz. PA achieves 24.84 adjacent channel leakage ratio less than -40.4 dBc for LTE signal 10-MHz...
This paper presents a fully integrated power amplifier (PA) using parallel-combined transistors with cascode adaptive biasing, implemented in standard 65 nm CMOS process. The the common-source stage linearizes effective gm. In addition, bias circuits are applied to both and common-gate stages provide optimum operation conditions each transistor, according output variations. When PA was tested modulation coding scheme 7 (MCS7) 802.11n signal, it meets −28 dB error vector magnitude spectral...
Abstract In this paper, we present a new framework to construct quantum circuit of S-boxes.We first model the circuits S-boxes based on Toffoli and linear layers. We generate vector spaces with values qubits used in layers apply them find circuits.Our technique by matching space's elements S-box's input output, meet-in-the-middle strategy.We applied our 4-bit S-boxes.While existing LIGHTER-R tools only that can be implemented 4 qubits, tool accomplishes same 5 qubits.Our also finds...
A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design the optimal impedance of PA (2 GHz/5 GHz PA) output transformers with low loss, which provided by 2:2 and 2:1 2 5 PA, respectively. In addition, several issues in WLP technology are addressed, method proposed. All considerations reflected procedure. The produces saturated 26.3 dBm peak power-added efficiency (PAE)...
Ransomware is malicious software that a prominent global cybersecurity threat. Typically, ransomware encrypts data on system, rendering the victim unable to decrypt it without attacker's private key. Subsequently, victims often pay substantial ransom recover their data, yet some may still incur damage or loss. This study examines Rhysida ransomware, which caused significant in second half of 2023, and proposes decryption method. employed secure random number generator generate encryption key...
In this paper, we present a new method to find Sbox circuits with optimal multiplicative complexity (MC), i.e., MC-optimal S-box circuits. We provide observations for efficiently constructing and computing MC, combined popular pathfinding algorithm named A*. our search, the A* outputs path of length corresponding an circuit. Based on in-depth analysis process enable function within graph investigate wider range S-boxes than existing methods such as SAT-solver-based tool [1] <bold...
In this article, we propose a methodology for finding impossible differential distinguishers permutations used in sponge-like constructions. Given the difference between typical block ciphers and such terms of key additions, initiate construction an trail starting from middle round. Based on proposed methodology, present several new or improved truncated Ascon, DryGascon, Sycon, Shamash all which were submitted to National Institute Standards Technology Lightweight Cryptography project. For...
In many lightweight cryptography applications, low area and latency are required for efficient implementation. The gate count in the cipher circuit depth must be to minimize these two metrics. Many optimization strategies have been developed linear layer, led by Boyer–Peralta (BP) algorithm. Advanced Encryption Standard (AES) has a focus of extensive research this area. However, while layer uses only XOR gates, S-box, which is an essential nonlinear component symmetric cryptography, various...
We present a fully integrated 2×2 MIMO CMOS LTE RF transceiver along with multi-band InGaP/GaAs HBT power amplifiers for LTE-A small cell (femtocell) base stations. The features highly LNAs and drive 24 individual I/O pins. PAs achieves ACLR <;-45dBc at 25dBm PAE >38% 33dBm by employing third-order intermodulation distortion (IMD3) canceling techniques. presented SiP composed of proposed radio shows plenty margins in conformal test femtocell station using commercial modem.
A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard technology. The transformer topology investigated to obtain a and high-linearity performance. By adopting 2:2 output transformer, an optimum impedance provided PA core. Besides, LC harmonic control block added reduce AM-to-AM/AM-to-PM distortions. produces saturated of 26.1 dBm with peak power-added efficiency (PAE) 38.2%. tested signal, it satisfies...
Multiplicative complexity is one of the important properties for efficiency S-box. In this paper, we present a new method to find S-box circuits with optimal multiplicative complexity. Our uses early abortion technique speed up finding canonical forms circuits. We adopted grouping AND gates and searching grouped parts. One or more component functions can be generated by each part, an all This allows wider range S-boxes investigated. believe that our will help designers generate efficient
Abstract ARIA is a block cipher proposed by Kwon et al. at ICISC 2003 that widely used as the national standard in Republic of Korea. Herein, we identify some flaws quantum rebound attack on seven‐round ARIA‐DM Dou and reveal limit this up to five rounds. Our revised applies not only but also ARIA‐MMO ARIA‐MP among PGV models, it valid for all key lengths. Furthermore, present dedicated attacks ARIA‐Hirose ARIA‐MJH first time. These are 256‐bit length because they constructed using degrees...
사물인터넷 기술의 발달로 인해 소형 컴퓨팅 장치가 보편화되고 있으며, 경량 환경에서의 정보보호를 위한 암호 알고리즘의 필요성이 대두되고 있다. HIGHT는 이러한 환경에 적합하도록 2006년 설계된 국산 알고리즘이다. 그러나 해당 알고리즘은 연관키 렉탱글 공격 기법을 사용해 전체 라운드 키 복구가 전수조사 시간 복잡도보다 빠르게 가능함이 이론적으로 밝혀진 바 본 논문에서는 FSE 2010에서 제안된 generalized feistel network의 optimal shuffle을 HIGHT의 구조에 적용한 HIGHT-variant의 안전성에 대해 논하며, 결과적으로 local collision 이용한 공격은 HIGHT-variant 분석에 효과적이지 않음을 보인다.