A UHF mobile single chip RFID reader is implemented in 0.18μm CMOS process. Developed IC achieves DA output power of 3 dBm, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OIP3</i> 14.8 phase noise -100 dBc/Hz at 100 kHz offset, figure 35.5 dB for talk mode, 6.2 listen before (LBT) and current consumption 108 mA from a 1.8 V supply. With an external PA, Tx generates 27 dBm with 42.5 dBm. leakage signal cancellation scheme employed to suppress...

For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The markets are maturing rapidly for applications such as cellular phones, car navigation, PMP so on. market drives low-cost, low-power small size significantly multiple functionality bands [1]. To meet the requirements, more integration of system blocks is needed. achieve this goal, 65nm CMOS multistandard multiband receiver SoC may be suitable solution.

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology WLAN CMOS PAs is proposed obtain broadband with compact using the wafer-level package technology. To achieve highly linear output high efficiency across 1-GHz bandwidth 5G-band PA, reconfigurable interstage matching transformer are proposed. For...

This paper provides a complex band-pass filter (BPF) for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia (T-DMB) tuner with I/Q gain phase mismatch calibration. calibration can be implemented in the first stage of BPF using feed-through resistor scheme. The automatic tuning circuit programmable clock is also presented. measurement results show 1.536 MHz bandwidth 2.048 IF center frequency 50 dB stop band attenuation at 0.7 offset. in-band out-band 3 <sup...

A new digital pixel driving scheme is presented for reducing power in the column-line drivers a single-pulse-PWM-based display. Rather than updating memory value every access of memory, proposed utilizes property that there are only two level transitions single-pulse PWM representing value. With use AND-embedded SRAM and simple logic controlling AND gates, this minimizes number signal as row-line scanning progresses. As result, dissipation greatly reduced compared to case using conventional...

A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven array micro-display panel. The based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias controlled to adjust pull-up strength inverters SRAM. This allows be operated with low-voltage row- and column-line signals while holding stored logic level. As result, power area driving circuits are greatly reduced. added do not necessitate overhead if pixels individually separated...

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated standard 40-nm CMOS process. In comparison transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, does so compact die area. With 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, PA achieves 19.7 15.7 dBm average output powers PAEs 17.1% 13%, HP LP respectively, while...

A direct-conversion satellite tuner-demodulator IC is realized using 0.18/spl mu/m CMOS technology. The down-converts a 950-2150MHz broadcasting signal to base band and demodulates the an MPEG data stream. conforms both DVB-S DSS standards. Experimental results show 9dBm IIP3 while consuming 230mA from 1.8V supply.

This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel-combined transistors and selective adaptive biasing. An bias circuit is applied to one of the take advantage both transistor method biasing at target output region. By using proposed biasing, can be maximized, resulting in higher added efficiency (PAE). The experimental results show that PA has saturated 26.9 dBm 2.48 GHz PAE 40.3% 3.3-V supply voltage. also tested modulation coding...

A 0.18μm CMOS dual-band low-IF mobile-TV tuner IC for T-DMB/DAB that supports Band-III and L-band is presented. By modifying a few metals via masks, the can support VHF UHF bands ISDB-T partial reception. The chip meets all specifications of both applications with sensitivity <-98dBm while consuming 100 mW from 1.8V supply occupying 3.4 X 3.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>

A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with auxiliary transistors extends the linear region further compared MGTR single transistor. Second, resistive source degeneration significantly suppresses unwanted 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -harmonic feedback effect caused by an inductive degeneration....

A CMOS analog front-end processor for a 4x speed CD-ROM is designed and fabricated in 0.8-μm process. The IC consists of RF amplifiers, pulse reshaping circuits, an automatic power control circuit laser diode, servo signal generator which includes track focus error detecting circuits. Experimental result shows that its performance enough 8x CD-ROM. enables to design true one chip or DVD player digital process technology.

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design the optimal impedance of PA (2 GHz/5 GHz PA) output transformers with low loss, which provided by 2:2 and 2:1 2 5 PA, respectively. In addition, several issues in WLP technology are addressed, method proposed. All considerations reflected procedure. The produces saturated 26.3 dBm peak power-added efficiency (PAE)...

A low power high linear transmitter for mobile WiBro and WiMAX is developed. The fabricated in a 0.18 μm 1P6M CMOS process characteristics SoC compatibility. To achieve linearity performance with consumption, the employs new linearization methods. Linear transconductor used mixer. utilizes negative feedback amplifier current mirror (CMA). In addition, multiple-gated transistor (MGTR) two auxiliary transistors resistive source degeneration are driver amplifier. With proposed techniques, of...

The 40nm CMOS WLAN transceiver which support 802.11 a/b/g/n/ac dual band with integrated power amplifier is implemented. covers 2.4GHz and 5GHz for 802. 11a/b/g/n/ac. wireless includes RF Transceiver, amplifier, LO generator high speed data converter. To achieve better phase balance lower consumption, the harmonic VCO frequency adopted were sufficiently isolated to prevent degradation of performance at power. compensate attenuation, LC tuning proposed. fabricated using process 5.4mm <sup...

A method for implementing a hardware‐efficient multi‐channel digital sigma‐delta modulator is presented processing field sequential multiple inputs. Compared to conventional one, which processes the inputs in time‐multiplexed manner without sharing integrator memory inputs, proposed significantly reduces number of storage bits by partially Simulation results on noise power spectral density and overall signal‐to‐noise ratio match well with those based quantitative analysis.

The numerical simulations were conducted on thermal environment with group installation of system air-conditioner outdoor unit. In this study, the effect air-guide unit and consequent performance improvement investigated. To validate present simulation, temperature around units was measured real fields where computational domain is considered in study. For commercial code ANSYS 15.0 used for flow solver. Cut-cell mesh method modeling unit, Semi-Implicit Method Pressure Linked...

The image rejection mixer for digital audio broadcasting and multimedia (DAB/DMB) is described. implemented in a 0.18mum six-layer metal CMOS process occupies 2.25mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To obtain the ultimate level of without additional tuning, double quadrature architecture used to linearize RF buffer, differential transconductance linearization technique (Tae wook Kim, et al., 2005). fabricated exhibits 65...

The 65nm CMOS wireless connectivity SoC which support 802.11 a/b/g/n, BT and NFC is implemented. cover 13.6MHz band for NFC, 2.4GHz 5GHz 802. 11a/b/g/n. includes RF Transceiver, Baseband modem ARM9 core with various peripherals. Soc fabricated using process 5.5 × mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. power consumption of 802.11n about 160mW 180mW receiver mode transceiver except PA respectively 170mW 190mW case....

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard technology. The transformer topology investigated to obtain a and high-linearity performance. By adopting 2:2 output transformer, an optimum impedance provided PA core. Besides, LC harmonic control block added reduce AM-to-AM/AM-to-PM distortions. produces saturated of 26.1 dBm with peak power-added efficiency (PAE) 38.2%. tested signal, it satisfies...

Abstract A new pixel circuit and a driving are proposed for high‐resolution field sequential color driven liquid crystal on silicon (LCoS) micro‐displays. The is based data storage with global charge transfer, whose reference node controlled to increase the LC voltage decrease response time. Pixel modulation adopted reduce size operation by half. This allows display be operated an overdrive scheme, at low‐voltages wide dynamic range. As result, circuits achieve low‐color crosstalk, both...