A5031500797- Quantum and electron transport phenomena
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design
- Quantum-Dot Cellular Automata
- Advanced DC-DC Converters
- Advancements in Semiconductor Devices and Circuit Design
- Magnetic properties of thin films
- Electromagnetic Compatibility and Noise Suppression
- Advancements in PLL and VCO Technologies
- VLSI and Analog Circuit Testing
- Analog and Mixed-Signal Circuit Design
- Embedded Systems Design Techniques
- Low-power high-performance VLSI design
- Formal Methods in Verification
- Reinforcement Learning in Robotics
- Robotic Path Planning Algorithms
- Advanced Data Storage Technologies
- Photovoltaic System Optimization Techniques
- Evolutionary Algorithms and Applications
New Mexico State University
2017-2022
Cairo University
2019
National Yang Ming Chiao Tung University
2019
Tokyo University of Science
2019
Traditional silicon binary circuits continue to face major challenges such as high leakage power dissipation and area of interconnections. Multiple-Valued Logic (MVL) nano-devices are two feasible solutions overcome these problems. In this paper, a novel method is presented design ternary logic based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties CNFETs adjusting Nanontube (CNT) diameters have desired threshold voltage having same...
Towards the goal of enhanced hardware security, this work proposes compact supervisory circuits to perform low-frequency monitoring a communication SoC. The RF output is monitored through an integrated envelope detector. input supply transceiver block SoC delivered by linear voltage regulator with current monitoring. These two are inexpensively fabricated in 0.6-μm technology. useful bandwidth detector measured as 1-6 GHz at 3.3 VDC and quiescent 2.65 mA. generates using 5 VDC, 1.83 mA, load...
Low-power designs are a necessity with the increasing demand of portable devices which battery operated. In many such operational speed is not as important life. Logic-in-memory structures using nano-devices and adiabatic two methods to reduce static dynamic power consumption respectively. Magnetic tunnel junction (MTJ) an emerging technology has advantages when used in logic-in-memory conjunction CMOS. this paper, we introduce novel hybrid MTJ/CMOS structure design AND/NAND, XOR/XNOR 1-bit...
Wireless communication protocols are used in all smart devices and systems. This work is part of a proposed supervisory circuit that classifies the operation SoC, particular, Bluetooth (BT) at low sampling frequency by monitoring RF output power input supply current. In essence, goal to inexpensively fabricate an envelope detector, current monitor, classifier on low-cost, low-frequency integrated circuit. When detects abnormal behavior, it can shut off BT chip. We extract simple descriptive...
Abstract A novel frequency‐to‐voltage converter based phase‐locked loop (PLL) is proposed to overcome the inability of a frequency‐locked lock phase. The dual‐loop PLL adds variable phase‐locking capability, such that phase locking angle can vary from 0–360°. additional be applied in data communication form modulation. design targeted for 0.5‐μm CMOS process. generates 480 MHz clock reference 15 MHz. In simulation, locks within 3.56 μs while consuming 1.61 mW power.
In this paper, we present an intelligent system where agents can co-ordinate creative tasks through machine learning and cooperation. For learning, used commonly pattern recognition algorithm - Principal Component Analysis (PCA). Based on recognition, plan a task that is performed by multiple agents. our case, to draw or perform art The action divided into three phases: obtaining design, composing mathematical model performing the case of co-ordination, various feedback techniques using...
A hybrid voltage-mode hysteretic boost converter is introduced in this work. The implemented control topology practically self-stabilized due to the introduction of a current-limiting loop. full range inductor current sensor and comparator are used realize zero detector also enable seamless transition from continuous discontinuous conduction mode. designed 0.5-μm CMOS process for an input voltage 3.2-4.2 V. regulates output 5 V while driving load 20-200 mA. minimum efficiency 93% achieved...
Low-power designs are a necessity with the increasing demand of portable devices which battery operated. In many such operational speed is not as important life. Logic-in-memory structures using nano-devices and adiabatic two methods to reduce static dynamic power consumption respectively. Magnetic tunnel junction (MTJ) an emerging technology has advantages when used in logic-in-memory conjunction CMOS. this paper, we introduce novel hybrid MTJ/CMOS structure design AND/NAND, XOR/XNOR 1-bit...
A new pulse width modulation (PWM)-based digital control for single-inductor multi-output (SIMO) DC-DC converters operating in continuous current mode (CCM) is proposed this paper.To reduce the complexity of system and hardware cost, only one digital-proportion-integration-differentiation (D-PID) compensator used SIMO converters, an idle period introduced between each phase to cross-regulation.Then, a buck switching converter using with two outputs designed implemented on field-programmable...
A novel frequency-to-voltage converter (FVC) based phase-locked loop (PLL) is proposed to overcome the inability of an FVC-based frequency-locked (FLL) lock phase. The dual-loop PLL adds variable phase-locking capability, such that phase locking angle can vary from 0o – 360o. additional be applied in data communication form modulation. design targeted for a 0.5-µm CMOS process. generates 480MHz clock reference 15MHz. In simulation, locks within 3.56 µs while consuming 1.61 mW power.