A5027129455- Advanced DC-DC Converters
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- COVID-19 Clinical Research Studies
- Advancements in Semiconductor Devices and Circuit Design
- SARS-CoV-2 and COVID-19 Research
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Multilevel Inverters and Converters
- Low-power high-performance VLSI design
- Calcium signaling and nucleotide metabolism
- Viral gastroenteritis research and epidemiology
- Advanced Battery Technologies Research
- Autophagy in Disease and Therapy
- Histone Deacetylase Inhibitors Research
- Computational Drug Discovery Methods
- VLSI and Analog Circuit Testing
- Electrostatic Discharge in Electronics
- Innovative Energy Harvesting Technologies
- Thermography and Photoacoustic Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- SARS-CoV-2 detection and testing
Intel (United States)
2023
New Mexico State University
2018-2022
Maxim Integrated (United States)
2020-2021
Cairo University
2019
National Yang Ming Chiao Tung University
2019
Tokyo University of Science
2019
A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 with a peak efficiency of 80% is implemented in 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator generates wide range switching frequencies proposed extend battery runtime. >70% for load currents the 12 17.8 mA achieved by implementing novel adaptively-biased pulse frequency modulation (ABPFM) technique controller. symmetric charge-discharge topology two-phase time interleaving...
Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and settling time. The uses an auxiliary feedback to increase the effective capacitance without loading output node. scheme validated in simulation by implementing driving 10 pF load capacitor 0.18 μm CMOS process. A detailed comparison of conventional nested Miller also presented. results showed reduction improvement rate compared other reported techniques literature.
A low-power pulse width modulation (PWM) control circuit for high-frequency switching direct current (DC)–DC converters based on a one-shot is proposed. The proposed PWM eliminates the use of high-power comparator and ramp generator that conventionally used to generate waveform. design validated through simulation in 0.13-μm process. operating at 20 MHz demonstrates greater than 20× reduction power consumption compared with conventional over duty-cycle range 10–90%.
Towards the goal of enhanced hardware security, this work proposes compact supervisory circuits to perform low-frequency monitoring a communication SoC. The RF output is monitored through an integrated envelope detector. input supply transceiver block SoC delivered by linear voltage regulator with current monitoring. These two are inexpensively fabricated in 0.6-μm technology. useful bandwidth detector measured as 1-6 GHz at 3.3 VDC and quiescent 2.65 mA. generates using 5 VDC, 1.83 mA, load...
A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 3.3 V to 1.5 with a peak efficiency of 68% is implemented in 2P3M 0.6-μm CMOS process 555 pF poly-poly flying capacitor and 1.34 nF MOS tank capacitor. This paper demonstrates means applying low-frequency input clock as part time-interleaving technique for symmetric charge-discharge topology reduces the output voltage ripple. Burst-mode pulse-frequency modulation used maintain high over wide range load currents....
A simplified model is described for a peak current-mode control boost converter. The proposed implemented by averaging the operating point of converter such that closed-loop stability can be analyzed. This behavior verified in simulation implementing 3.9 V input to 5 output with 240 mA load current. simulations showed good matching ac response and step response, detailed analysis presented.
A frequency spectrum segmentation methodology is proposed to extract the response of circuits and systems with high resolution low distortion over a wide range. achieved by implementing modified Dirichlet function (MDF) configured for multi-tone excitation signals. Low attained limiting or avoiding spectral leakage interference into interest. The use window allowed further reduction in suppressing system-induced oscillations that can cause severe while acquiring This MDF generates an...
A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that critical in design of amplifiers. The allows obtaining closed-form expression poles and zeros due to elements along conventional zeros. This gives an additional degree freedom choosing location improve frequency response. validated simulation by implementing voltage follower 0.18-μm CMOS process. shows existence zero introduced at high-frequencies it implementation.
We present an all-digital voltage droop monitor (VDM) with coupled ring-oscillators (CoRO) for accurate in-situ monitoring every clock cycle. Measurements from a 3.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> testchip in Intel 4 CMOS containing 9 3-way CoRO and baseline RO VDMs demonstrate 3X improvement resolution $(\sim 2.6$ mV/b) over the baseline. In addition, measurements show $3 \sigma$ uncertainty (repeatability) error of...
A new pulse width modulation (PWM)-based digital control for single-inductor multi-output (SIMO) DC-DC converters operating in continuous current mode (CCM) is proposed this paper.To reduce the complexity of system and hardware cost, only one digital-proportion-integration-differentiation (D-PID) compensator used SIMO converters, an idle period introduced between each phase to cross-regulation.Then, a buck switching converter using with two outputs designed implemented on field-programmable...