A5101759515- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and interfaces
- Electronic and Structural Properties of Oxides
- Nanowire Synthesis and Applications
- Metal and Thin Film Mechanics
- Ferroelectric and Piezoelectric Materials
- Copper-based nanomaterials and applications
- E-commerce and Technology Innovations
- Climate Change Policy and Economics
- Microwave Engineering and Waveguides
- Copper Interconnects and Reliability
- Semiconductor Quantum Structures and Devices
- Adaptive optics and wavefront sensing
- HVDC Systems and Fault Protection
- Energy, Environment, Economic Growth
- Optical Coatings and Gratings
- Big Data and Business Intelligence
- Collaboration in agile enterprises
- Radio Frequency Integrated Circuit Design
- Calibration and Measurement Techniques
- Infrared Target Detection Methodologies
- Thin-Film Transistor Technologies
Tianjin University of Technology
2024
Xi'an Institute of Optics and Precision Mechanics
2024
Chinese Academy of Sciences
2011-2024
Anhui Jianzhu University
2024
Dalian Maritime University
2015-2018
Massachusetts Institute of Technology
2013-2016
Nankai University
2010-2016
Soochow University
2011-2014
Shanghai Institute of Microsystem and Information Technology
2012-2013
Shijiazhuang Tiedao University
2010
We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables precise design length thickness allows careful balancing performance against short-channel effects. demonstrate L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =70 nm InAs MOSFETs with 5 feature record g...
A novel SOI MOSFET structure to suppress the floating-body effect (FBE) and short-channel effects is proposed successfully demonstrated. In new structure, a tunnel diode body contact embedded in source region, which can effectively release accumulated carriers. an nMOSFET, heavily doped p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> layer introduced beneath n region so that are connected through tunneling. The fabricated device shows...
Vertical quantum-well (QW) tunnel-FETs are fabricated based on an ultrathin In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/GaAs xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Sb staggered gap (type-II) heterostructure lattice matched to InP. Area-dependent QW-to-QW tunneling current is demonstrated. Devices with HfO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>...
Commercial complexes integrate various business formats, and a fire outbreak can lead to widespread, continuous, chain-reaction social disturbances, including severe casualties, economic losses, impacts. To deeply explore the characteristics influencing factors of accidents in urban commercial China, this study first analyzed accident cases that occurred from 2002 2022. Using mathematical statistics, analysis examined year month accidents, their severity, causes identify key risk associated...
DC and RF characterization up to 10 GHz from RT T = 77 K combined with detailed modeling are used for the first time in a comprehensive investigation of impact gate efficiency on subthreshold swing (SS) Quantum-well Tunnel-FETs (QWTFETs). Calibrated experimental InGaAs/GaAsSb QWTFETs based IV, CV measurements full quantum-mechanical (QM) simulations suggest that only 55% voltage contributes tunneling current modulation which results degraded switching steepness. This is due coupling junction...
The effect of NH3 plasma treatment on the interfacial property between ultrathin HfO2 and strained Si0.65Ge0.35 substrate has been investigated by high-resolution cross-sectional transmission electron micrographs, x-ray photoelectron spectroscopy, VBS, capacitance-voltage (C-V), current density-voltage (J-V). TEM XPS results confirm that layer with N–Hf N–Si/O-N-Si bonds acts as a barrier against interdiffusions during annealing in some degree. valence-band offsets ΔEV HfO2/SiGe interfaces...
The device leakage current and the ON-state characteristics of In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunneling field-effect transistors (QWTFETs) are examined on basis temperature-dependent measurements. Different from commonly observed Shockley–Reed–Hall (SRH) recombination in OFF-state, substrate is identified as source OFF-current, which limits steepness transfer characteristics. In addition, analysis TFET operation linear regime reveals a barrier due to an ungated region near drain,...
The performance of In 0.53 Ga 0.47 As/GaAs 0.5 Sb quantum‐well tunnel field‐effect transistors (TFETs) for microwave‐frequency detection is explored experimentally. strong nonlinearity the TFET transfer characteristic, which arises from a combination band‐to‐band tunnelling between source and channel gate modulation junction, can be utilised high‐sensitivity microwave detection. Using an analytical model, it shown that current sensitivity approximately proportional to second‐order derivative...
There are usually three methods for supplier slecetion, they have their own characteristics and suitable different environmental requirements. In real economic activity, selection take place in the environment with insufficient information, evaluation indicators of which show both quantitative qualitative characteristics. Grey system theory solved issues under circumstances limited data incomplete or inadequate information. It can whiten quantify grey indicators, effectively reduce...
A tunnel diode body contact (TDBC) SOI structure is presented as a means to suppress the floating effect in partially depleted (PD) p-MOSFETs. Experiments using phosphorus implantation were carried out form source region. Tunnel embedded region, which can effectively release accumulated carriers. The fabricated device shows suppressed expected. new does not enlarge size and fully compatible with CMOS technology.
Tunneling field-effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of subthreshold swing conventional devices enabling lower power electronics. However, as shown in TFET review by Seabaugh and Zhang [1], experimental characteristics not achieved steepness theoretical predictions. Possible explanations non-abrupt turn-on include long band-tails (exacerbated doping) that extend into semiconductor band gap, mid-gap interface...
For a very thin dielectric MOS capacitor, the influence of interface layer on capacitance extraction is not negligible. We report new correction method for capacitor based five-element model, which includes capacitance, parallel resistance, series and resistance. This needs to combine double-frequency C-V I-V measurement data. By comparing impedance model with that two-element we have five characteristic equations. From these equations, deduce five-degree equation then provide accurate...
The effects of working pressure on the composition, structure and surface morphology properties CuInSe2 (CIS) films selenized with a plasma-assisted selenization process is investigated. Higher selenium content, better crystalline quality much more regular particles compared to others are found in CIS film 40 Pa pressure. A Cu(In,Ga)Se2 device fabricated optimized demonstrated be than our previous result. After discussion, reason for these phenomena attributed compromise electron temperature...
This paper has done some research on how to scientifically find the order parameters which influenced supply chain system's collaborative operation. Besides revealing thinking process of collaboration management, we tried use simulation technology build intelligent model management. On this background, Model Drive Decision Support System (MDDSS) was built, and its working principle interpreted. The will provide a new perspective way framework for theory practice as well development systems.
A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well fast write speed. operation power dissipation dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance nondestructive read operation.