A5083523986- Interconnection Networks and Systems
- Advanced Memory and Neural Computing
- Software-Defined Networks and 5G
- VLSI and FPGA Design Techniques
- Supercapacitor Materials and Fabrication
- Ferroelectric and Negative Capacitance Devices
- Advancements in Battery Materials
- Advanced Optical Network Technologies
- Advanced Wireless Communication Techniques
- Parallel Computing and Optimization Techniques
- Advanced Sensor and Energy Harvesting Materials
- Error Correcting Code Techniques
- Advanced Materials and Mechanics
- Dielectric materials and actuators
- Neural Networks and Reservoir Computing
- Advancements in Photolithography Techniques
- Neural Networks and Applications
- Graphene research and applications
- Retinal Development and Disorders
- Image and Video Quality Assessment
- Industrial Automation and Control Systems
- Microwave Imaging and Scattering Analysis
- ECG Monitoring and Analysis
- Coding theory and cryptography
- Image Enhancement Techniques
MediaTek (Taiwan)
2021-2024
Ming Chi University of Technology
2024
National Sun Yat-sen University
2020
ETH Zurich
2019
National Taiwan University
2010-2018
Baylor College of Medicine
2010-2012
To interact naturally and achieve mutual sympathy between humans machines, emotion recognition is one of the most important function to realize advanced human-computer interaction devices. Due high correlation involuntary physiological changes, signals are a prime candidate for analysis. However, due need huge amount training data high-quality machine learning model, computational complexity becomes major bottleneck. overcome this issue, brain-inspired hyperdimensional (HD) computing, an...
Tiny-machine learning (TinyML) and artificial intelligence-of-things (AIoT) present new opportunities for machine-intelligent applications with stringent energy constraints. To conserve system energy, high-power devices stay dormant are woken up only when an event is detected by a low-power always-on detector: which can be implemented analog compute in memory (ACIM). However, there tradeoff between the inference accuracy nonideality ACIM designs, limiting applicable AIoT applications....
Network-on-chip systems can achieve higher performance than bus for chip multiprocessor systems. However, as the complexity of network increases, channel and switch congestion problems become major bottlenecks. An effective adaptive routing algorithm help minimize path through load balancing. conventional schemes only use channel-based information to detect status. Due lack switch-based information, is difficult reveal real status along path. Therefore, in this paper, we remodel show hidden...
Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With increasing number of cores scaling network in deep submicron (DSM) technology, NoC systems become subject to manufacturing defects have low production yield. Due fault issues, reduction available routing paths packet delivery may cause severe traffic congestion even a system crash. Therefore, fault-tolerant algorithm desired maintain correctness functionality. To overcome...
Compressive sensing (CS) is attractive in long-term electrocardiography (ECG) telemonitoring to extend life-time for resource-constrained wireless wearable sensors. However, the availability of transmitted personal information has posed great concerns potential privacy leakage. Moreover, traditional CS-based security frameworks focus on secured signal recovery instead privacy-preserving data analytics; hence, they provide only computational secrecy and have impractically high complexities...
Enhancing video quality is critical for achieving a boosted user experience on smart devices including mobiles, televisions, and monitors. Practical hardware designs should deliver high performance with minimal resources under the stringent limitations related to bandwidth, area energy budget. The widespread usage of deep-learning algorithms in image processing tasks, super-resolution (SR) noise-reduction (NR), has further emphasized necessity energy-efficient solutions. Therefore, an...
The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems using die stacking recent days. Because of larger power density and heterogeneous thermal conductance different silicon layers 3D NoC, problems NoC become more exacerbated than that 2D a major design constraint for high-performance system. To control system temperature under certain limit, many Dynamic Thermal Managements ( <italic...
The regular topology of mesh-based network-on-chip (NoC) provides flexible and scalable architecture for chip multiprocessor (CMP) systems. However, as the complexity network increases, routing problems become performance bottlenecks. In field wide area networks (WANs), ant colony optimization (ACO) has been applied to an adaptive improving achieving load balancing. Nevertheless, if we directly apply ACO NoC systems, implementation cost is excessively high. To overcome this problem,...
The advanced deep submicrometer technology increases the risk of failure for on-chip components. In network-on-chip (NoC) systems, constrains bandwidth and network throughput. Fault-tolerant routing algorithms aim to alleviate impact on performance. However, few works have integrated congestion-, deadlock-, fault-awareness information in channel evaluation function avoid hotspot around faulty router. To solve this problem, we propose ant colony optimization-based fault-aware (ACO-FAR)...
Ant Colony Optimization (ACO) is a problem-solving technique that was inspired by the related research on behavior of real-world ant colony. In domain Network-on-chip (NoC), ACO-based adaptive routing has been applied to achieve load-balancing effectively with historical information. However, cost ACO network pheromone table too high, and this overhead grows fast scaling NoC. order fix problem, it essential model algorithm in more careful consideration system architecture, available hardware...
The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because die stacking. Besides, for high-performance requirement, the minimal adaptive routing algorithms result in unbalanced traffic load and worse temperature distribution system. On other hand, conventional selection strategies determine path based on information, which leads to unawareness potential hotspot huge performance impact. To solve problems, this paper, we first define a novel...
The partially adaptive routing plays an important role in the performance of Network-on-Chip (NoC). It uses information network to select a better path deliver packet. However, it may have imbalanced diversity different directions, which makes their tolerances traffic load differ lot from each other. This characteristic would cause problems balancing but give us extra network. To achieve balancing, this paper, we present scenario with Path-Diversity-Aware (PDA) and Augmented-PDA (A-PDA)...
The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because die stacking and different conductance between layers. Up to now, most previous works cannot further achieve balance the 3D NoC since they consider either only temperature or traffic information. We propose a Proactive Thermal-Dynamic-Buffer Allocation (PTDBA) scheme constrain routing resource around overheated regions. In addition, we reduce frequency packets switching in router By doing...
The network-on-chip (NoC) system can provide more scalable and flexible on-chip interconnection compared with bus. performance of adaptive routing algorithms greatly relies on the adopted network information. To best our knowledge, previous utilize either spatial or temporal information to improve performance. However, few works have established a framework analyzing nor showed how integrate In this paper, we define region (NIR) for NoC systems. NIR indicate arbitrary combinations...
This paper presents a Digital Compute-In-Memory design in 12nm FinFET technology with capacity to store weights for 16 kernels per input channel. macro is designed using an 8T SRAM push-rule foundry bitcell integrated kernel selection and multiplication AI Edge application that achieves 30% better TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without loss of TOPS/W than comparable logic-rule custom based architecture on the...
Networks-on-Chip (NoC) provides a regular and scalable design architecture for chip multi-processor (CMP) systems. The Ant Colony Optimization (ACO) is distributed algorithm. Applying ACO to selection models of adaptive routing can improve NoC performance. Currently, ACO-based only uses the historical traffic information. While additional temporal spatial information better approximation network status global load-balancing. In this paper, we first consider enhancement congestion We propose...
The technology of software-defined networking (SDN) facilitates network management by adopting a controller to direct the operations switches. This paper aims efficiently manage flows in multi-domain SDN-based (MDS) network, where each domain (i.e., subnetwork) is governed and there exist links between domains. To improve MDS performance, cooperative flow (CFM) framework proposed paper. Each finds paths for its such that loads can be balanced. When some are still congested but no substitute...
Brain-inspired Hyperdimensional computing (HDC) has shown its effectiveness in low-power/energy designs for edge the Internet of Things (IoT). Due to limited resources available on devices, multi-task learning (MTL), which accommodates multiple cognitive tasks one model, is considered a more efficient deployment HDC. However, as number increases, MTL-based HDC (MTL-HDC) suffers from huge overhead associative memory (AM) and performance degradation. This hinders MTL-HDC practical realization...