In this brief, a cobweb-based redundant through-silicon-via (TSV) design is proposed with efficient hardware as well high repair rate to clustered faulty TSVs (FTSVs). The experimental simulation results demonstrate that for highly faults, the of RTSV method 48.59% and 1.75% higher than ring-based router-based methods, respectively. Furthermore, can achieve 63.93% 16.34% reductions compared design,

The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well double-node (DNUs), are typical This article proposes two radiation-hardened FF designs, namely DNU-tolerant (DUT-FF) and DNU-recoverable (DUR-FF). First, the DUT-FF which mainly consists four dual-interlocked-storage-cells (DICEs) three 2-input C-elements, is proposed. Then, provide complete self-recovery from DNUs, DUR-FF...

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. this paper, we propose a novel latch, namely MURLAV, protected against quadruple node-upsets (QNUs) environments, as well an algorithmic error-recovery method. latch provides complete recovery from all...

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The comprises three interlocked single-node-upset-resilient cells and each of the mainly consists mutually feeding back Muller C-elements. Simulation results demonstrate double-node upset resilience 73.0% delay-power-area product saving on average compared with up-to-date DNURL designs.

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a cost and double-node-upset (DNU) completely (LCDNUT) design is proposed. The mainly comprises storage module (SM) feeding back to 3-input C-element. SM consists of eight input-split inverters. Since the inputs C-element cannot be simultaneously flipped, tolerates any DNU in SM. When single node output are affected, can self-recover from DNU. Second, tolerate triple-node-upset (TNU), by...

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against The mainly consists series mutually interlocked 3-input Muller C-elements (CEs) that forms circular structure. output any CE in respectively feeds back one...

Aggressive technology scaling makes modern advanced SRAMs more and vulnerable to soft errors such as single-node upsets (SNUs) double-node (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled (QCCS) second Sextuple (SCCS). The QCCS cell comprises four cross-coupled input-split inverters keep stored values, provides self-recoverability from SNUs at low cost. To improve reliability, SCCS uses six construct a large error-interceptive feedback loop hence...

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) widely used to address these concerns. MTJs nonvolatile (NV) compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant NV latch, i.e., M-TPDICE-V2, providing high reliability. addition, further an advanced namely, M-8C, that is able completely...

The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between main and processor. processing in-memory (PiM) capabilities of emerging nonvolatile devices have potential to partially alleviate problem. In this brief, we use ferroelectric field-effect transistor (FeFET), one devices, design a multifunctional cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well content searching ternary content-addressable...

Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it promising candidate replace complementary metal oxide semiconductor (CMOS) Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD (XS-3DAs). We use ripple-carry (RCA) parallel...

In harsh radiation environments, nanoscale CMOS latches have become more and vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm technology. The proposed is mainly constructed seven mutually feeding-back soft-error-interceptive modules (SIMs), of which consists two three-input C-elements one two-input C-element. Due mutual feedback mechanism SIMs dual-level soft-error...

With the rapid advancement of CMOS technologies, nano-scale latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node (QNUs). The is mainly constructed from three dual-interlocked-storage-cells (DICEs) triple-level soft-error interceptive module (SIM) consists six 2-input...

Due to the winding level of thinned wafers and surface roughness silicon dies, quality through-silicon vias (TSVs) varies during fabrication bonding process. If one TSV exhibits a defect its manufacturing process, probability multiple defects occurring in TSVs neighboring faulty increases, i.e., tend be clustered, which significantly reduces yield 3-D integrated circuit. To resolve clustered faults, router-based, ring-based, group-based, cellular-based redundant (RTSV) architectures were...

The continuous advancement of CMOS technologies makes SRAMs more and sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) Double-node (DNUs). First, the that has redundant nodes access transistors is proposed. following advantages: (1) it can self-recover all possible SNUs; (2) a part DNUs; (3) small overhead in terms power dissipation. Then, reduce read write time,...

This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, QRHIL that mainly consists a 5×5 looped C-element matrix is proposed. Then, to reduce overhead, uses 24 interlocking C-elements Both latches can self-recover from any QNU, while has low cost compared QRHIL. Simulation waveforms show...

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. this article, a latch design protected against MNUs in the harsh radiation as well an algorithm-based verification process is proposed. Due...

Traditional username and password-based single-factor authentication is easy to deploy but vulnerable dictionary attacks, snooping, brute force attacks. Two-factor (2FA) has been proposed improve the security, where smart devices are used as second factor. However, interaction between human device required, which inconvenient users. In addition, an attacker able get factor through fraud, thus invalidating current 2FA mechanisms. order solve these problems, we propose a transparent two-factor...

In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback Muller C-elements, the internal nodes output node are self-recoverable from single event upset (SEU), i.e. particle striking induced logic upset, regardless energy particle. The offers much wider spectrum working clock frequency on account smaller delay insensitivity high impedance state. performs with lower costs...

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The is mainly constructed from eight mutually feeding back C-elements any node pair of the DNU self-recoverable. Using speed transmission path clock gating technique, has dissipation. Simulation results demonstrate self-recoverability also show that delay-power-area product improved approximately by 81.80% on average, compared with latest designs.

In this brief, a non-invasive online solution for 2.5D IC based on distributed pulse shrinking is proposed to test the faults of interconnects. Furthermore, regression model artificial neural network (ANN) in order judge whether interconnects are faulty and quantify degree real time by monitoring delay Experiments defect detection presented through HSPICE simulation with realistic models 45nm CMOS technology. The results show that method has features including: high resolution, low area...

Through-silicon-vias (TSVs) are prone to defects during the manufacturing process, which pose yield challenges for three dimensional integrated circuits (3D-ICs). The area per TSV is too great be ignored, and in order not use any redundant TSVs, a chain-type time division multiplexing access (TDMA)-based fault tolerance technique proposed. However, double-TSV structure used group, resulting significant hardware overhead under given large-scaled circuit design. Furthermore, it impossible...

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with C-element. Due to the existence of sufficient feedback loops, latch can achieve complete DNU toleration. Second, an improved DNUCT (referred as TNUCT latch) by inserting redundant level C-elements at output stage intercept node-upset errors accumulated in upstream DICEs so completely tolerate any possible triple-node-upset...

This paper presents two novel memory cell designs that can completely tolerate double-node upsets. First, a layout dependent is proposed. Since the has many redundant storage nodes, achieves following robustness: 1) In case of 1 being stored, self-recover from any upset (DNU) as well single node (SNU); 2) in 0 double-adjacent-node (DANU), partial double-separated-node (DSNU) SNU. Any other DSNU be tolerated by due to use approach. Second, layout-independent proposed DNU Simulation results...

Due to the winding level of thinned wafers and surface roughness silicon dies, through-silicon vias (TSVs) defect tend be clustered, reducing yield 3-D integrated circuit significantly. To tackle this fault clustering problem, existing TSV repair methods adopt redundancy idea, which brings a major cost integration. In brief, honeycomb-TDMA design is proposed mitigate impact multiple clustered faults without need redundant TSVs (RTSVs), thereby decreasing area overhead enhances yield. The...

With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., voters), that have very small overhead compared with traditional voters. The proposed Advanced...