A5086400318- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Nanowire Synthesis and Applications
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Quantum Structures and Devices
- Quantum and electron transport phenomena
- Topological Materials and Phenomena
- Advanced Semiconductor Detectors and Materials
- Physics of Superconductivity and Magnetism
- Advancements in Photolithography Techniques
- 2D Materials and Applications
- Advanced Surface Polishing Techniques
- Social and Educational Sciences
- Advanced biosensing and bioanalysis techniques
- Electronic and Structural Properties of Oxides
- Silicon Carbide Semiconductor Technologies
- Magnetic and transport properties of perovskites and related materials
Microsoft (United States)
2023
Delft University of Technology
2021
QuTech
2021
Lund University
2014-2020
Informa (Sweden)
2018
Nano Hydrophobics (United States)
2017-2018
IBM Research - Zurich
2017
Topological phases of matter can enable highly stable qubits with small footprints, fast gate times, and digital control. These hardware-protected must be fabricated a material combination in which topological phase reliably induced. The challenge: disorder destroy the obscure its detection. This paper reports on devices low enough to pass gap protocol, thereby demonstrating gapped superconductivity paving way for new qubit.
Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there large discrepancy between measured simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated characterized. The structure, composition, strain characterized using transmission electron microscopy emphasis...
Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break thermionic 60 mV/decade of subthreshold swing (SS) metal oxide semiconductor (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) ferroelectrics has a promising performance booster MOSFETs to bypass aforementioned fundamental limit exploiting differential amplification gate voltage...
We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and maximum oscillation 155 GHz. The transistor has transconductance 730 mS/mm is based arrays nanowires gate-all-around high-κ gate dielectric. Furthermore, small-signal modeling shows ~80% reduction the total parasitic capacitance when metal pad overlap in transistors reduced through additional patterning.
We present a vertical nanowire InAs/GaAsSb/GaSb TFET with highly scaled InAs diameter (20 nm). The device exhibits minimum subthreshold swing of 48 mV/dec. for V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> = 0.1–0.5 and achieves an I xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> 10.6 μA/μm xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> 1 nA/μm at 0.3 V. lowest achieved is 44 0.05 Furthermore, benchmarking performed...
Tunnel field-effect transistors with ability to operate well below the thermal limit (with a demonstrated 43 mV/decade at VDS = 0.1 V) are characterized in this paper. Based on 88 devices, impact of low subthreshold swing overall performance is studied. Furthermore, correlation between parameters that important for device characterization determined.
In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- off-current levels of TFETs with staggered source/channel band alignment. Experimental results from lateral shown, as well first on integration vertical Si substrates.
We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.3 V, was for a device with 20-nm InAs diameter. ON-current the same 35 μA/μm xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> 0.5...
We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability reach a point subthreshold swing of 35 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.05 V. Furthermore, the impact drain, channel, source scaling on currents are studied. Impact gate-overlap is more evident for devices highly due strong reduction current. small...
Abstract Semiconducting–superconducting hybrids are vital components for the realization of high‐performance nanoscale devices. In particular, semiconducting–superconducting nanowires attract widespread interest owing to possible presence non‐abelian Majorana zero modes, which quasiparticles that hold promise topological quantum computing. However, systematic search Majoranas signatures is challenging because it requires reproducible hybrid devices and reliable fabrication methods. This work...
We present a simple model to evaluate the sharpness of band edges for tunnel field-effect transistors (TFETs) by comparing subthreshold swing and conductance in negative differential resistance region. This is evaluated using experimental data from InAs/InGaAsSb/GaSb nanowire TFETs with ability reach well below thermal limit. A device lowest swing, 43 mV/decade at 0.1 V, exhibits also sharpest band-edge decay parameter E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present a detailed analysis of low-frequency noise (LFN) measurements in vertical III-V nanowire tunnel field-effect transistors (TFETs), which help to understand the limiting factors TFET operation. A comparison with LFN metal-oxide semiconductor same channel material and gate oxide shows that these TFETs is dominated by properties, allowed us optimize junction without deteriorating performance. By carefully selecting heterostructure materials, we reduced inverse subthreshold slope well...
Tunnel field-effect transistors (TFETs) are promising candidates that have demonstrated potential for and beyond the 3 nm technology node. One major challenge TFETs is to optimize heterojunction high drive currents while achieving steep switching. Thus far, such optimization has mainly been addressed theoretically. Here, we experimentally investigate influence of source segment composition on performance vertical nanowire InAs/InGaAsSb/GaSb TFETs. Compositional analysis using transmission...
In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, level impacts both off-state and on-state performance these devices. Separation heterostructure improved subthreshold swing The best devices reached a point 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation had significant impact due effects...
A method to fabricate inorganic vertical spacer layers with well-controlled thickness down 40 nm using electron beam exposure is demonstrated. These spacers are suitable in nanowire transistor configuration. As material, the authors use hydrogen silsesquioxane (HSQ), a material low permittivity and high durability. They show that resulting HSQ can be controlled by dose used it also depend on initial of layer. To achieve good reproducibility, found necessary fully submerge nanowires beneath...
We present measurements and simulations of semiconductor-superconductor heterostructure devices that are consistent with the observation topological superconductivity Majorana zero modes. The fabricated from high-mobility two-dimensional electron gases in which quasi-one-dimensional wires defined by electrostatic gates. These enable local non-local transport properties have been optimized via extensive to ensure robustness against non-uniformity disorder. Our main result is several devices,...
In this work, we experimentally report the figures of merit state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough maintain excellent over a large range even in devices with number arrayed nanowires (here, 4 184 per device), accounting technological variability. The investigated FETs have...
We report on the fabrication of molybdenum (Mo) nanopillar (NP) arrays with NP diameters down to 75 nm by means deep-reactive ion etching at cryogenic temperatures. A variable-thickness Mo metal layer sputtered onto a Si3N4/Si substrate makes possible NPs different lengths in controllable manner. demonstrate how our strategy leads tunable cross-sections geometries, including hexagonal, cylindrical, square and triangular shapes, using electron beam lithography hydrogen silsesquioxane negative...
By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well charge partitioning vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> is found to largely dominate ON-state TFETs, whereas gate-to-source sufficiently small be completely dominated by parasitic components. This indicates that junction on source...
Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction oxide-interface traps their performance. After careful fitting a minimum set parameters, effects diameter scaling gate alignment predicted. Trap-assisted tunneling at oxide interface is suppressed into volume-inversion regime. Gate steepens slope increases ON-current. The 'trap-tolerant' device geometry can result in small sub-threshold swing...
Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD.The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxideinterface bulk traps device characteristics.Simulated temperature-dependent transfer curves in good agreement with measured data which validates simulation set-up.It found that trap-assisted tunneling involving adjacent to hetero-junction primarily responsible for degradation...
We present RF characterization of vertical gate-all-around InAs nanowire MOSFETs integrated on Si substrates with peak f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> = 142 GHz and xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> 155 GHz, representing the record for transistors. The devices has an Lg ≈ 150 nm a g xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> =700 mS/mm diameter 38 EOT 1.4 nm. high values is achieved through...
Vertical InAs/GaSb nanowire TFETs with diameters of 20 nm and 25 have been fabricated characterized. The influence diameter, gate-placement, numbers studied. best device shows a subthreshold swing 68 mV/dec at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.3 26 μA/μm xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> 0.5 V. It achieves self-gain larger than 100 high transconductance efficiency.
Single gate oxide defects in strongly scaled Tunneling Field-Effect Transistors with an inverse subthreshold slope well below 60 mV/decade are investigated by Random Telegraph Signal (RTS) noise measurements. The cause for RTS electrons being captured and released from individual the oxide. Under assumption that elastic tunneling is underlying capture emission mechanism, measured time constants vary relative position of channel Fermi level defect energy while amplitudes - independent release...