Wireless communication now has the speed and power to converge seamlessly with other consumer business electronics. However, battery technology not kept pace advancement in circuit technology. As a result, design of management is becoming more complex problem for this new generation wireless devices converged voice, data, multimedia. In paper, highly integrated IC (PMIC) presented which enables mobile that are cost effective, thinner compact better efficiency. The overall architecture system...

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as multipliers. Compared to digital multipliers, CTT-based multiplier shows significant area and power reduction. The composed of a scalable array energy efficient analog-digital interfaces. By implementing the sequential fabric, engine's mixed-signal interfaces simplified hardware overhead remains constant regardless size array. A proof-of-concept...

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending sweep of continuous wave, detecting power level at the receiver side, then adapting modulation scheme, data bandwidth, carrier frequencies accordingly based on detected information. supported scheme ranges from nonreturn to zero/Quadrature phase shift keying...

This paper presents a millimeter-wave (127 GHz) CMOS transceiver with digital pre-distortion capable PAM-4 modulator for contactless communications. The transmitter upconverts modulated baseband signals through free-running 127-GHz oscillator and single-balanced mixer, it delivers carrier to folded-dipole antenna, which is designed on FR408HR substrate. receiver's low-noise amplifier provides 10-dB gain, the self-mixer downconverts carrier-modulated without necessity of synchronization....

A CMOS low-noise amplifier (LNA) for ultrawideband universal radio is presented. Based on capacitive cross-coupled dual-g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -enhancement topology, the circuit topology could be reconfigured as different versions single-ended or differential inputs. One possible input/output resonant scheme analyzed and may help LNA to exhibit input matching, low noise, flat gain in an ultra-wide frequency...

In this article, 150-GHz CMOS transmitter (TX) and receiver (RX) are presented for contactless plastic waveguide communications. The implemented system employs a four-level pulse-amplitude modulation (PAM-4) noncoherent detection. direct upconversion TX self-mixing RX suffer amplitude nonlinearity distort the carrier-modulated multilevel signals. A current-mode digital predistortion is integrated in PAM-4 modulator to correct signaling. Coupling antennas designed on FR4-HR substrates. same...

This brief presents a capacitor digital-to-analog converter (DAC) based technique that is suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode. Detailed comparisons between the proposed and conventional direct-coupling-based as well resistor-DAC-based techniques are given, revealing potential benefits terms of speed, linearity, implementation complexity, also power consumption. A PAM-4 with 2-Tap feed-forward equalization adopting implemented 65-nm CMOS...

This paper presents the concept and design of a wideband merged LNA mixer covering frequency range from 2GHz to 10GHz using standard 0.18-μ m CMOS technology. Gm-boosting current bleeding techniques are adopted make proposed single stage topology suitable for high conversion gain, low noise power consumption operation. A peaking technique further broadens working front-end up 10GHz. achieves 20dB flat figure 6.7~8.5dB over whole an input IP3 -1dBm. It consumes only 7.2mW 1.8V supply.

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator noise, including supply-induced extracted from phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in domain. The receiver prototype fabricated 65nm CMOS technology achieves reduction −88 −109dBc/Hz at 1MHz offset, an integrated (IPN) −16.8 −34.6dBc, when operating 2.4GHz.

Contactless chip-to-chip or board-to-board proximity (~1mm) communications have been realized by using either wireless transmission [1-3], inductive/capacitive coupling schemes [4-6]. However, their practical deployments in consumer electronics are currently limited because of bandwidth-density-inefficient OOK/ASK-only modulations process/voltage/temperature sensitive carrier-recovery-less coherent detection [1], and large coupler footprint (6~10mm <sup...

In order to optimise the activation process, effect of three processes on direct electroless nickel–phosphorous plating AZ91D was studied. The properties coating and Ni–P were characterised with electrochemical tests, SEM EDX. results showed that an optimum for nickel deposition developed via twice activations K 4 P 2 O 7 NH HF respectively. first in solution could clean surface remove Mg 3 (PO ) dust produced by pickling. proper 1·12–1·49 F/ ratio (at-%) composed MgF MgO or Mg(OH) second...

In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed operates in background and extracts RO as well supply-induced from the digital phase-locked loop. obtained information then used to restore randomly rotated baseband signal domain. A receiver prototype fabricated standard 65-nm CMOS technology. It demonstrates reduction -88 -109 dBc/Hz at 1-MHz offset an integrated -16.8 -34.6 dBc when operating 2.4 GHz.

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed integrated with 4-GHz random-matrix clock generator, enabling physical speed up to 500 MS/s 40.2-dB SNDR in NS-mode an equivalent 4 GS/s 36.2-dB CS-mode, leading FOMs of 239 fJ/conversion-step 71 fJ/conversion-step, respectively. passive-charge-sharing open-loop...

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method optimize operating frequency, band-width as well power consumption proposed. This based on bipolar device characteristics, whereby a negative resistance model can be used estimate optimal normalized upper and lower dividers under different conditions, which conventionally ignored literatures. provides simple but efficient procedure designing high performance for...

This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed terms of its speed, power consumption, linearity. voltage-mode PAM-4 2-tap FFE utilizing the architecture implemented 65-nm CMOS technology. It achieves data rate 34 Gb/s an energy efficiency 2.7 mW/Gb/s.

This paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2×8 master-slave hierarchical interleaved architecture is employed. complementary dual-loop-assisted buffer proposed to achieve both high linearity and bandwidth with low power. achieves 38.4-dB SNDR 50-dB SFDR a Nyquist input at sampling rate consumes 83.4 mW, resulting 140 fJ/conv.-step Walden FOM buffers.

151 GHz CMOS transmitter and receiver are presented for ultra-short distance (~1 mm) contactless connection plastic waveguide communications. To continue to scale the communication bandwidth, 4-level pulse amplitude modulation (PAM-4) is utilized by implementing a current-mode PAM-4 modulator in transmitter. The suffer non-linear characteristics create distortions on signaling. A digital pre-distortion circuit integrated correct such system non-idealities. antennas realized FR4HR substrate...

The paper presents a natural tree species recognition methods based on YOLOv7. We propose new small target detection layer the YOLOv7 network, use improved Mosaic-8, and introduce attention mechanism. On basis of not affecting speed YOLOv7, we improve accuracy. Experiments show that method has stronger learning ability, accuracy than other algorithms under same conditions.

This paper presents a 0.9GHz-10GHz Ultra Wideband Low Noise Amplifier (LNA) designed for software-defined-radios (SDR). Capacitive cross coupling (CCC) is used at both input stage and cascade wideband impedance matching small noise figure (NF). A combination of inductor peaking load series between the stages LNA employed flat gain enhanced matching. implemented in standard 0.18μm CMOS technology. For ultra applications, it achieves maximum 14dB, 3.5dB~4.1dB NF +1.8dBm IIP3. It consumes...

A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or trigger circuits, n-type lightly doped drain p-type halo-assisted SCR has a voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> as low 7 ESD robustness exceeding 50 mA/mum, which enables effective Compared with traditional low-voltage-triggered SCR,...

This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within predriver stage for multitap multilevel signal summation in charge domain at the front end. Such unique approach isolates summing node from output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling level-shifting without sacrificing its speed. A level-mismatch-correction scheme is adopted effectively enhance signaling quality. Implemented 28-nm CMOS,...

Single-oxidant slurries are prevalently utilized in chemical and mechanical polishing (CMP) of 4H-SiC crystal. Nevertheless, it is a challenge to achieve high material removal rate (MRR) surface quality using single oxidant meet the needs global planarization damage-free nanoscale processing SiC wafers. To solve this challenge, novel method proposed for CMP double slurry. This slurry mainly consists alumina (Al

Based on the emergence and development of autonomous driving technology, identification obstacles road is a very important challenging task. And there are many difficulties in realization this task, for example, types targets, scale span large. In view these problems, experiment proposes three improvement directions YOLOv3 algorithm to perform task target prediction: one improve up-sampling multiple use more shallow spatial information accuracy small detection. The second change way feature...

A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge the that arises from seemingly unrelated change hydrogen anneal back end. physical mechanism leading interaction metal layout are presented.