A5056353738- Analog and Mixed-Signal Circuit Design
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Neuroscience and Neural Engineering
- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies
- Advanced Memory and Neural Computing
- Sensor Technology and Measurement Systems
- CCD and CMOS Imaging Sensors
- Advanced Sensor and Energy Harvesting Materials
- Radio Frequency Integrated Circuit Design
- Electrostatic Discharge in Electronics
- EEG and Brain-Computer Interfaces
- Antenna Design and Analysis
- Parallel Computing and Optimization Techniques
- Advanced MRI Techniques and Applications
- Semiconductor Lasers and Optical Devices
- Thermography and Photoacoustic Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Digital Filter Design and Implementation
- ECG Monitoring and Analysis
- Microwave Engineering and Waveguides
- Industrial Vision Systems and Defect Detection
- Advanced Antenna and Metasurface Technologies
- Sparse and Compressive Sensing Techniques
Delft University of Technology
2018-2025
BioElectronics (United States)
2021
Marmara University
2020
Lund University
2010-2012
École Polytechnique Fédérale de Lausanne
2006-2010
University of Southern California
2008
Southern California University for Professional Studies
2008
Aksaray University
2004
Niğde Ömer Halisdemir Üniversitesi
2004
The Ohio State University
2004
Abstract Silicon integrated circuits (ICs) are central to the next-generation miniature active neural implants, whether packaged in soft polymers for flexible bioelectronics or implanted as bare die probes. These emerging applications bring IC closer corrosive body environment, raising reliability concerns, particularly chronic use. Here, we evaluate inherent hermeticity of ICs, and examine potential polydimethylsiloxane (PDMS), a moisture-permeable elastomer, standalone encapsulation...
Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In circuit delay, hence leakage consumption depends on supply voltage exponentially. By reducing idle time of both that realizes and can be reduced. This paper presents an in-depth comparison synchronous asynchronous techniques for their efficiency. First, transistor level accurate high model is developed techniques. Afterwards, using model, reduction due investigated...
This paper addresses the design of self-timed energy-minimum circuits, operating in sub-VT domain. The presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, fully-decoupled latch controller has been developed, which integrates circuitry. outlines corresponding flow, is based on contemporary synchronous EDA tools, transforms design, into circuit. flow current-sensing technique validated by an asynchronous version...
This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined operate in the subthreshold regime. The applicable on gate-level netlists, where back-annotated toggle information used find minimum operation point, corresponding maximum clock frequency, as well dissipated per cycle. application model demonstrated by exploring efficiency pipelining, retiming, and register balancing. Simulation results, obtained during...
A compact, low-loss and narrowband dual-mode microstrip filter is proposed using degenerate modes of a patch resonator loaded with two narrow slots. The structure fed by inset lines connected directly to the centre adjacent edges notches. verified both simulation measurement.
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely subtraction and absolute value based algorithmic conversion. simulation is done using standard CMOS 65 nm process. least-significant-bit resolution designed 200 ps outputs 7-bit digital words with an ENOB 6.2 bits. dynamic range TDC 25.4 ns core consumes 38 μW from supply...
For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within corrosive environment body still remains a critical challenge. chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility barrier properties. Yet, for evaluation packaging prediction, conventional helium leak test method can no longer be applied due to mm-size such implants. Alternatively, accelerated soak studies are...
This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate efficiency standard-cell designs, over several CMOS technology generations, from 180 65 nm, operated in sub-threshold domain. The simulation results indicate nm low-leakage high-threshold (LL-HVT) as favourable choice. Accordingly, design fabricated LL-HVT CMOS. Measurements validate and prove that circuit is fully functional...
This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using conventional 1.8 V, 0.18 mum digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3 ps peak-to-peak) chip-level clock distribution ensured by five-level balanced tree, implemented in low swing current-mode logic. The block achieves peak SFDR 71.3 dB and 9.26 ENOB at MS/s, with an input signal 1.5 Vpp. measured 200 78 dB, while SNDR...
Abstract Digital circuits operating in the sub‐threshold regime are able to perform minimum energy operation at a given delay. In circuit delay, and hence, leakage consumption depend on supply voltage exponentially. By reducing idle time of circuit, energy‐minimum can be reduced, resulting lower consumption. This paper first presents an model for comparing synchronous asynchronous operation. After presentation model, design simulation results novel current sensing based completion detection...
In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in of pipelines can be realized. The system very simple, consisting sensor transistor, basic AC-coupled amplifier and monostable multivibrator. proposed easily integrated into CMOS design flow. advantages shown through simulations on an 16-bit ripple carry adder standard 0.18 mum process operating at 400 mV...
This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) region with throughput and supply voltage constraints. A 12-bit filter is implemented along various unfolded structures, used to form a decimation chain. The designs are synthesized 65 nm low-leakage CMOS technology threshold voltages. sub-V model applied characterize...
In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in pipelines can be realized. The system very simple, consisting sensor transistor, basic AC- coupled amplifier and monostable multivibrator. proposed easily integrated into CMOS design flow. advantages shown through simulations on an 8-bit ripple carry adder standard 0.18/irre process...
This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial (ANN) with Softmin-based activation function is described as implementation example. To realize operation, presented makes use monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The ANN was designed in standard CMOS 0.18 μm IC process operates...
This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, presented implementation makes use monostable multivibrator based analog-to-time converters, fixed-width pulse generators, basic digital gates and asynchronous time-to-digital converter. The was designed in a standard 0.18 μm IC process operates from supply voltage 0.6V. is to accommodate data 128 individual...
A novel active-RC biquad is presented which can be reconfigured as a polyphase filter for low IF wireless receiver architecture, and lowpass zero architecture. second order lowpass-polyphase reconfigurable implemented to illustrate the technique. 1.8 V fully differential operational amplifier in 0.18 /spl mu/ CMOS technology used active element.
In this paper the advantages of using differential cascode voltage switch pass gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families compared in terms their performance and energy-delay-product (EDP) figures. Multiple gates were simulated 0.18 mum technology. Simulation results show that DCVSPG NAND2 has 71%, NOR2 82% full adder 66% EDP savings over counterparts
In this study, the internal or superficial cracks that may occur during production of ceramic plates were determined using impact noise method.In industry, materials are frequently used in areas such as kitchenware and construction.Many different methods quality control processes materials.In sound produced by applied to material was analyzed.As a result analysis, found be undamaged damaged.This method is called Impulse Noise damaged with selected pendulum.The application have same...
This study addresses the design of self-timed energy-minimum circuits, operating in sub-VT domain and a generic implementation template using bundled-data circuitry current sensing completion detection (CSCD). Furthermore, fully decoupled latch controller was developed, which integrates with current-sensing circuitry. Different configurations that utilise proposed are highlighted. A contemporary synchronous electronic automation tools-based flow, transforms into corresponding circuit, is...
This paper presents an analysis on energy dissipation of a digital half band filters operated in the sub-threshold (sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) region with throughput constraints. The degradation speed sub-V domain is counteracted by unfolding architectures. A filter implemented basic 12-bit and its various unfolded structures. designs are synthesized 65 nm low-leakage high-threshold CMOS technology. model...