A5084481086- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Electromagnetic Compatibility and Noise Suppression
- 3D IC and TSV technologies
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Model Reduction and Neural Networks
- Integrated Circuits and Semiconductor Failure Analysis
- Natural Language Processing Techniques
- Face recognition and analysis
- Face and Expression Recognition
- Online Learning and Analytics
- Interconnection Networks and Systems
- Video Surveillance and Tracking Methods
- Topic Modeling
- Radio Frequency Integrated Circuit Design
- Embedded Systems Design Techniques
- Anomaly Detection Techniques and Applications
- Multimodal Machine Learning Applications
- Advanced Vision and Imaging
- Cryptographic Implementations and Security
- Human Pose and Action Recognition
- Radiation Effects in Electronics
Beijing Normal University
2013-2024
China Medical University
2024
Ministry of Education of the People's Republic of China
2017
Florida International University
2008
Tsinghua University
2002-2006
Infineon Technologies (Germany)
2006
IBM (United States)
2006
Chinese Academy of Sciences
2005
Institute of Computing Technology
2002-2005
Semiconductor Research Corporation
2005
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power devices for both general applications. Utilizing plasma nitrided gate oxide, off-set slim spacers, advanced co-implants, NiSi temperature MOL process, well designed NMOSFET PMOSFET achieved significant improvement from the previous generation, especially has demonstrated an astonishing 35 % enhancement node.
BN-containing molecules have attracted great attention in the past few decades due to their intriguing electronic and optoelectronic properties. Herein, three novel functionalized Donor-Acceptor (D–A) type luminophores, i.e., aminoboranes containing...
Attendance is an important part of classroom evaluation. This paper develops a university automatic attendance system by integrating two deep learning algorithms MTCNN face detection and Center-Face recognition. A large number experimental results show that: (1) The can record such three violations discipline for attendance, that absence, lateness leaving early. An table about all students status after class immediately recorded. (2) identifies faces very fast needing only 100 milliseconds...
Unlike terrestrial radio frequency communication, acoustic waves are major communication means in underwater networks. Unfortunately, incur long propagation delays that must be considered the media access control (MAC) design to achieve a high throughput. Another reason for low throughput is almost all modems operate under half-duplex mode. For increasing throughput, several full-duplex proposed. However, most current MAC protocols designed not suited modems. Toward proper approach, this...
In this work, we study learning behavior analysis for automatic evaluation of the classroom teaching. We define five behaviors including listen, fatigue, hand-up, sideways and read-write, construct a class-room dataset named as ActRec-Classroom, which includes categories with 5,126 images in total. With aid convolutional neural network (CNN), propose system framework. Firstly, Faster R-CNN is used to detect human body. Then OpenPose extract key points skeleton, faces fingers. Finally, CNN...
In this paper, we present an efficient method to budget on-chip decoupling capacitors (decaps) optimize power delivery networks in area way. Our algorithm is based on gradient-based non-linear programming for searching the solution. contributions are gradient computation (time-domain merged adjoint network) and a novel equivalent circuit modeling technique speed up optimization process. Experimental results demonstrate that capable of efficiently optimizing very large scale P/G networks.
Attendance is an important part of daily classroom evaluation.This paper develops automatic attendance system by integrating two deep learning algorithm Faster R-CNN face detection and SeetaFace recognition algorithm.The results numerous experiments indict that: (1) the can record such five violations classroom, that absence, later arrival, early departure, free access, carelessness for attendance, give table which reflect situation all students after school.(2) For small classrooms with...
We present an efficient method to budget on-chip decoupling capacitors (decaps) optimize power delivery networks in area way. Our algorithm is based on gradient-based nonlinear programming for searching the solution. contributions are gradient computation (time-domain merged adjoint network) and a novel equivalent circuit modelling technique speed up optimization process. Experimental results demonstrate that capable of efficiently optimizing very large scale P/G networks.
We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled pFET performance gain 15% over non-graded eSiGe control. When combined compressive stress liner (CSL), the drive current reached 770muA/mum at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> = 100nA/mum V xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> 1V. Competitive nFET...
In today's power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the oxide layer thickness continues to shrink below 20Å. As a result, decaps will become leaky due from CMOS devices. this paper, we take first look at in P/G optimization. We propose model for practical also present new two-stage leakage-current-aware approach efficiently optimize networks...
In today's power/ground (P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the oxide layer thickness continues to shrink below 20/spl Aring/. As a result, decaps become leaky due from CMOS devices. this paper, we take first look at in P/G optimization. We propose model for practical also present new two-stage leakage-current-aware approach efficiently optimize...
This paper proposes a new simulation algorithm for analyzing large power distribution networks, modelled as linear RLC circuits, based on partial random walk concept. The method has been shown to be an efficient way solve small number of nodes in larger network by H.-F. Qian et al. (2003), but the becomes expensive that are more than few. We combine direct methods like LU factorization with concept networks when significant node waveforms is required. also apply equivalent circuit modelling...
This paper presents an efficient method to analyze power distribution networks in the time-domain. Instead of directly analyzing integration approximated power/ground at each time step as previous methods did, new first builds equivalent models for many series RLC-current chains based on their Norton's form companion original networks, and then precondition conjugate gradient (PCG) iterative is used solve reduced networks. The solutions are back solved from that Our contribution introduction...
Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, delay-fault pattern sets of ISCAS89 benchmarks, algorithm can cut down 37.5% or more than the simulation-based annealing algorithm. Second, because approaches which use Hamming distance between two input patterns, to optimize power, cannot reduce as much ISCAS85 benchmarks expected, a novel approach that uses an ideal circuit without delay, is presented. Experimental results demonstrate our...
Motion estimation (ME) is one of the bottlenecks in terms computational cost a video encoder system. In this paper, we present cost-effective method to calculate "Vector Edge" current frame. We store all vectors' information within frame and put them Laplacian Gaussian edge detection operator. It similar image but need consider two vectors instead one, which different from luminous detection.The experiments show that proposed luminance based graphic because doesn't go off with high light or...
As transistor size continues to scale down, leakage power has become a critical issue of integrated circuit design. The maximum total current, which is mainly determined by the sum subthreshold, gate and reverse biased junction BTBT an important parameter guide low-leakage high-performance designs. Up now, how estimate current accurately within endurable time remains unsolved. Precise simulators can calculate accurately, but are only practical for small circuits. In this paper, fast...
Leakage power has become a more and significant issue of VLSI industry as technology scales. Input vector control is an efficient method to reduce leakage current when circuit operating in standby mode can be widely used because its easy implementation little influence on the original circuit. Fast simulators are urgently needed generate minimum pattern (MLP), which applied suppress current. Precise (such HSPICE) accurately account for estimation, but only practical small circuits. In this...
Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as cost effective approach. A stress-proximity-technique (SPT) explored to improve device without adding process complexity. Record drain currents of 840/490 μA/μm have achieved for NMOS and PMOS, respectively, at 1.2V off-leakage current 1nA/μm. Junction profiles optimized reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO integrated into this technology first time, offering...
In this paper, we propose an efficient statistical analysis method for analyzing on-chip power grids. The new method, called SN-SOR (and its faster version, PSN- SOR), is based on a novel localized relaxed iterative approach and it can perform variational one node at time. PSN-SOR further speeds up the by using refined conditioner, where initial solution of used as pre-conditioner later iterations. Experimental results show that about two orders magnitude(186X) than Monte- Carlo with slight...