A5073419986- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Nanowire Synthesis and Applications
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- Biodiesel Production and Applications
- Lubricants and Their Additives
- Fluid Dynamics Simulations and Interactions
- Analog and Mixed-Signal Circuit Design
- Cavitation Phenomena in Pumps
- Advanced biosensing and bioanalysis techniques
- Fluid Dynamics and Heat Transfer
- Catalysis and Hydrodesulfurization Studies
- Analytical Chemistry and Sensors
- Spacecraft and Cryogenic Technologies
- Ferroelectric and Negative Capacitance Devices
- Lattice Boltzmann Simulation Studies
- Silicon and Solar Cell Technologies
Lovely Professional University
2022-2024
Thapar Institute of Engineering & Technology
2019-2021
Indian Institute of Technology Roorkee
2016-2017
Panjab University
2015
This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of silicon body referring to rectangular core–shell (RCS) architecture. The use RCS has significantly reduced induced drain leakage and therefore, obtaining improved performance parameters. It is observed parasitic BJT action gets diminished architecture due enlargement tunneling width at channel/drain interface. Further, after validating our simulations experimental...
Abstract A new state of the art double gate junctionless transistor (DGJLT) namely rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate performance. An RCS-DGJLT device using a visual technology computer aided design tool and look up table-based Verilog-A model has been carry out spice simulation circuit. Device shows extraordinary performance when compared conventional DGJLT. The exhibits an OFF current ( I off ) ∼10 −14 A, ON on −5...
A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom device called as core–shell (RCS-DGJLT). The doping thickness are optimized to improve performance of RCS-DGJLT. for different thicknesses has not been explored yet literature. An interesting observation found that should be equal smaller thicknesses, whereas thicker required larger thicknesses. RCS-DGJLT shown remarkable improvement than DGJLT. Further, effect misalignment...
In this paper, a multi-gate junctionless field-effect transistor with quad gate and multiple channels has been proposed thoroughly simulated. The device offers lower Ioff current of 4.34 × 10−19 A, an Ion 4.17 10−06 A Ion/Ioff ratio 9.65 1012, threshold voltage 0.86 V, transconductance 5 10−05 S, drain-induced barrier lowering (DIBL) 22 mV/V, subthreshold slope (SS) 61.51 mV/dec. visual contour plots the are also included in study to understand working mechanism. larger tunneling width...
The short channel effects and performance parameters of double gate junctionless transistor are analyzed at different lengths. In this paper various graphs like Drain Induced Barrier Lowering, Subthreshold Swing, On current, Off on/off ratio Threshold voltage variations lengths discussed. Junctionless is a new technology device with no junctions the easy fabrication when scaling done. Reasons for (20nm, 25nm 30nm) Double Gate provides better control over carriers flowing in device, as front...
This paper describes different architectures of a rectangular core shell double gate junctionless field effect transistor (RCS-DGJLT). The device performance has been studied when the either same or opposite type doping to shell. It is found that an RCS-DGJLT with oppositely doped without heavily source/drain (S/D) extension regions exhibits OFF current ~10−14A and ON ~10−5A. In addition, S/D placements dopant concentration in region explored, so control charge carriers during states can be...
The impression of gate dielectric and spacer on the performance rectangular core shell double junctionless transistor (RCS-DGJLT) using extensive simulations is studied. RCS-DGJLT brings captivating response in terms device. effect studied for first time RCS-DGJLT. device gets improve increasing constant till thickness (tcore) = 3 nm (tshell) 4 nm. However, beyond nm, degrades much high k dielectric. Further, enhanced tcore > higher reducing doping. also by incorporating spacers. It has been...
The performance of p and n-type rectangular core shell double gate junctionless field effect transistor (RCS_DGJLT) on varying oxide thickness is studied. plays a vital role to achieve good capacitance. impact short channel effects also varied from 0.5nm 2nm in both RCS-DGJLT. the device increasing observed be almost same for types device. devices analyzed basis different parameters like OFF current, ON ON/OFF current ratio, subthreshold slope threshold voltage. It that 1nm gives better...
In this paper, enhancement of volume depletion is studied on P-type double gate junctionless Field Effect Transistor (P-DGJLFET) by Gate work function and dielectric engineering. The formation parasitic BJT action in device along with DIBL effect curtailed integrating Rectangular Core-Shell (RCS) architecture varying core doping different oxides electrodes, respectively. After validating our simulations the experimental results Junctionless FET, we demonstrated that RCS based P-DGJLFET high...
The simulation and drawing based on new type of technology namely junction less transistor CMOS inverter is discussed in this paper at various channel lengths. transient curve, noise margin, differences between conventional has been illustrated paper. surface conduction bulk steps using visual TCAD also expressed. designing fabrication along with the pros cons have characterized. short parameter which all other parameters directly or indirectly depends calculated for both different nodes....
The correlation between silicon thickness and work function difference plays an important role to achieve best performance of field effect transistor. In this paper, a p-type double gate junctionless transistor (DGJLT) is studied by varying the thickness. Further, interesting observation related material made. parameters device are observed for lesser However, on increasing can be maintained tuning material. basis different like OFF current, ON ON/OFF current ratio, subthreshold slope (SS)...
The performance of the newly proposed inverted T-shaped heterojunction FinFET ($\perp$-FinFET) with concept oxide stacking (L-FinFET_OS) is discussed and compared conventional FinFET. device has been evaluated based on several important parameters, including ON current, OFF current ratio (ON/OFF), subthreshold slope, transconductance, threshold voltage, drain-induced barrier lowering. results this analysis demonstrate that performs well across all these parameters. It observed in structure,...
Analog design is still a challenge for designer working at lower technology node due degradation in devices and circuit performance increased short channel non ideal effects. Medical equipment needs high gain low noise amplifier frequently medical data acquisition signal processing. CMOS differential amplifiers are suitable choice its value of gain, margin CMRR. Multiple stages further improve but the cost other analog performance. Use VT transistors preferred transistor connected to input...
The Performance of gate misaligned N-type conventional double junctionless field effect transistor (JLFET)and rectangular core-shell (RCS) based JLFET is studied. misalignment the studied towards source side. performance parameters analyzed are ON current, OFF ON/OFF current ratio, Subthreshold slope and threshold voltage. These “Figure Merits” compared with under same conditions misalignment. proposed RCS structure exhibits superior perfectly aligned condition less sensitive to as compare...
The performance of N-type double gate junctionless Field Effect Transistor(JLFET) at different silicon thickness is studied using TCAD simulations. the device highly dependent on thickness. parameters like ON current, OFF ON/OFF current ratio, Subthreshold Slope(SS) and threshold Voltage has been varied from 6nm to 12nm. It observed simulations that with increase in degraded. best are obtained when 6nm. This paper also demonstrates correlation between work function for better performance....
In this paper, an analytical, detailed two-dimensional potential profile model of a newly proposed rectangular core-shell-based double-gate junctionless metal oxide semiconductor (RCS-DGJLMOS) is presented. A numerical solution the presented for conventional n-type MOS (DGJLMOS), and changes made in RCS-DGJLMOS are extensively While solving 2-D Poisson equations, parabolic assumed along silicon thickness both devices. The characteristics studied on varying doping concentrations, dielectric...