Fanruo Meng

ORCID: 0000-0003-2876-2798
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About
Contact & Profiles
Research Areas
  • Advanced Memory and Neural Computing
  • Adversarial Robustness in Machine Learning
  • Ferroelectric and Negative Capacitance Devices
  • Advanced Neural Network Applications
  • Semiconductor materials and devices
  • Biometric Identification and Security
  • Advancements in Semiconductor Devices and Circuit Design
  • Cancer-related molecular mechanisms research
  • Face recognition and analysis
  • Face and Expression Recognition
  • Integrated Circuits and Semiconductor Failure Analysis
  • Circular RNAs in diseases
  • RNA modifications and cancer

University of Delaware
2018-2022

Henan Provincial People's Hospital
2021

Henan University
2021

University of Electronic Science and Technology of China
2017

CircPVT1 is demonstrated to promote cancer progression in esophageal squamous cell carcinoma (ESCC). However, the role and potential functional mechanisms of circPVT1 regulating 5-fluorouracil (5-FU) chemosensitivity remain largely unknown.ESCC cells resistant 5-FU were induced with continuous increasing concentrations step-wisely. A counting kit-8 assay was used analyze viability ESCC cells. LDH release kit evaluate cytotoxicity. RT-qPCR assess expression level non-coding RNAs cDNAs....

10.3389/fonc.2021.780938 article EN Frontiers in Oncology 2021-12-13

Hardware accelerators built with SRAM or emerging memory devices are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on resource-constrained devices. After deployment, however, performance these is threatened by faults in their on-chip and off-chip memories where millions DNN weights held. Different types may exist depending underlying technology, degrading inference accuracy. To tackle this challenge, paper proposes an online self-test framework that...

10.1145/3394885.3431519 article EN Proceedings of the 28th Asia and South Pacific Design Automation Conference 2021-01-18

Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on resource-constrained embedded devices. While facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in on-chip off-chip memories, where millions weights held. The use emerging Non-Volatile Memories (NVM) further exposes a non-negligible rate permanent defects due immature fabrication, limited endurance, aging. To tolerate NVM-based...

10.1145/3477016 article EN ACM Transactions on Embedded Computing Systems 2021-09-22

Neural networks (NNs) have become the go-to tool for solving many real-world recognition and classification tasks with massive complex data sets. These require large sets training, which is usually performed on GPUs CPUs in either a cloud or edge computing setting. No matter where training performed, it subject to tight power/energy storage/transfer constraints. While these issues can be mitigated by replacing SRAM/DRAM nonvolatile memories (NVMs) offer near-zero leakage power high...

10.1109/tcad.2018.2858360 article EN publisher-specific-oa IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018-10-16

As Deep Neural Networks (DNNs) are widely adopted in many real-world applications, their integrity becomes critical. Unfortunately, DNN models not resilient to fault injection attacks. In particular, recent work has shown that Bit-Flip Attack (BFA) can completely destroy the intelligence of DNNs with a few carefully injected bit-flips. To defend against this threat, we propose Light-weight Integrity MArks (LIMA) framework which protects most significant bits (MSBs) weights - main target BFA....

10.1109/host49136.2021.9702292 article EN 2021-12-12

The application of convolution neural network provides numerous opportunities to get performance face recognition boosted. These require efficient deep structures as well optimization methods for large datasets. However, existing mainly focus on stacking more convolutional layers while ignoring the importance width. In this work, we review concept depth and width sum up relationship between these two factors in network. As a result, an optimal method is proposed designing: can be...

10.1109/iscas.2017.8050275 article EN 2022 IEEE International Symposium on Circuits and Systems (ISCAS) 2017-05-01

Hardware accelerators are essential to the accommodation of computation and memory-intensive neural network (NN) applications on resource-constrained edge devices. While hardware facilitate fast energy-efficient convolution operations, their accuracy is threatened by various types faults in on-chip off-chip memories, where millions NN weights held. To achieve in-time fault detection, a self-test process that periodically runs small set test images accelerator can be adopted. This paper...

10.1109/isvlsi54635.2022.00076 article EN 2022-07-01
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