A5038709211- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Optical Sensing Technologies
- Ocular and Laser Science Research
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Fluorescence Microscopy Techniques
- Magnetic Field Sensors Techniques
- Thin-Film Transistor Technologies
- Silicon Carbide Semiconductor Technologies
- Semiconductor Quantum Structures and Devices
- Advanced Memory and Neural Computing
- Non-Destructive Testing Techniques
- Electrical and Bioimpedance Tomography
- Electronic and Structural Properties of Oxides
- Silicon and Solar Cell Technologies
- Analytical Chemistry and Sensors
- CCD and CMOS Imaging Sensors
- Advanced Fiber Laser Technologies
- GaN-based semiconductor devices and materials
- Plasmonic and Surface Plasmon Research
- Radio Frequency Integrated Circuit Design
- Electric Motor Design and Analysis
- Nanowire Synthesis and Applications
- Radiation Effects in Electronics
- Perovskite Materials and Applications
Nanjing University of Posts and Telecommunications
2016-2025
Qingdao University of Technology
2024
Applied Materials (United States)
2020
Nanjing University
2010-2019
Collaborative Innovation Center of Advanced Microstructures
2017-2019
Shandong University of Science and Technology
2016
Beijing Microelectronics Technology Institute
2002-2010
Institute of Microelectronics
2006
Cypress Semiconductor Corporation (United States)
2004
De Montfort University
1997-2003
An amine-free method is used to systematically investigate the role of Cs, Pb and Br in hot-injection synthesis.
This paper presents a new modeling and simulation method to predict the important statistical performance of single photon avalanche diode (SPAD) detectors, including detection efficiency (PDE), dark count rate (DCR) afterpulsing probability (AP). Three local electric field models are derived for PDE, DCR AP calculations, which show analytical dependence key parameters such as triggering probability, impact ionization distributions that can be directly obtained from Geiger mode Technology...
All-inorganic CsPbX3 (X = Cl, Br, I) perovskite nanocrystals (NCs) are highly attractive due to their outstanding optical and electrical properties. However, poor stability easy anion exchanges between with different halides limit applications in light-emitting diodes (LEDs). To solve the problems, we developed an approach situ synthesize NCs into porous silica colloidal spheres, which can effectively prevent exchange increase photo stability. Based on our results, first proved that is...
An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, covers voltage dependent non-linear effects, geometrical temperature effects and packaging stress influences, only includes small number of physical technological parameters. In addition, the structure relatively simple, consisting passive network eight resistances, four current-controlled sources parasitic capacitances. The has been written Verilog-A hardware...
A compact high-speed active quenching and recharging circuit (AQRC) is proposed for single-photon avalanche diode (SPAD) detectors fabricated in standard 0.18 μm CMOS technology. novel sensing scheme employed to speed up the process of detection, enabling a low afterpulsing probability high photon-counting rate. The simulation experimental results indicate that time reduced down 0.7 ns maximum rate close 200 Mcps (counts per second), meanwhile as 0.75% obtained. Due configuration, area...
Timing jitter as a key performance of single-photon avalanche diode (SPAD) detectors plays significant role in determining the fast temporal response behavior SPAD device. Nevertheless, few analytic models are developed to directly calculate characteristic timing for its modeling difficulty. In this paper, we propose simple method, which can predict SPADs, without using time-consuming Monte Carlo simulation. Model investigation incorporates current, buildup time, and tail under different...
This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. monolithic chip features highly sensitive horizontal switched plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like achieves magnetic sensitivity low offset. A new spinning current modulator stabilizes the quiescent output improves reliability conditioner. The tested results show that at 5...
Multi-frequency Terahertz (THz) detectors have shown great application potentials in THz imaging and sensing systems. For the first time to our knowledge, a novel dual-frequency detector with stacked structure consisting of silicon-based plasmonic antenna metal-based one compact unit is proposed fabricated standard CMOS technology. Compared metal antenna, based on heavy-doped poly-silicon materials enables excite localized surface plasmon resonance mode, making effective absorption waves...
The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source capacitance reduction technique by shifting the source lightly doped drain region and analyze effectiveness on improved complementary (CMOS) terahertz (THz) detectors. It is experimentally found that for 0.65-THz integrated CMOS detector, maximum improvement voltage responsivity noise-equivalent power can be 155%...
AlGaN/GaN FinMISHFETs with m-plane sidewall surface channel and various fin widths (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> ) were fabricated characterized. The investigated devices have much higher current drivability due to the uniform smooth of than those a-plane channel. Wfin smaller 36 nm exhibit normally-off operation, high Ion/Ioff ratio 108, remarkable subthresholdswing (SS) 40 mV/decade in wide range at least three...
This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, formation 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation 2DEG sidewall MOS channels at positive threshold voltage normally off operation. The channel starts forming in middle fin, whereas edges are depleted lateral...
Abstract In this paper, a series of preliminary experimental data for wave (current)-induced hydrodynamics, pore-water pressure and scour around an exposed pipeline is presented. Unlike previous studies, the combined action waves currents considered in study. Wave flume experiments were conducted to investigate temporal spatial variations pressures seepage, as well development pipeline. The results indicate that seabed response caused by are significantly different from those load alone. It...
A monolithic low-voltage H-bridge brushless DC (BLDC) vibration motor driver with an integrated high sensitivity Hall sensor has been presented in 0.18 μm high-voltage complementary metal-oxide semiconductor technology. To improve the start-up reliability, a full-on start mode is applied to realise high-speed sequence by shortening time. Meanwhile, active function activated prevent dead point phenomenon if magnet pole sensed built-in does not change during starting. This complete one-chip...
In this paper, we investigate the influence of deep level defects on electrical properties Ni/4H–SiC Schottky diodes by analyzing device current–voltage (I–V) characteristics and deep-level transient spectra (DLTS). Two barrier heights (SBHs) with different temperature dependences are found in diode above room temperature. DLTS measurements further reveal that two kinds Z1/2 Ti(c)a located near interface between Ni SiC energy levels EC–0.67 eV EC–0.16 respectively. The latter one as ionized...
A novel Time-to-Amplitude Converter (TAC) based on Sample and Hold (S/H) principle is presented for single photon time-of-flight (TOF) measurement. With a high fill factor as much 34% avalanche diode (SPAD) pixel, the designed TAC offers potential to realize high-density time-correlated counting (TCSPC) detectors. Post-layout simulation reveals that time resolution of 195 ps LSB obtained over 100 ns full-scale range (FSR). Furthermore, characterized by low differential nonlinearity (DNL)...
This paper presents a new analytical geometry optimization model to depict the optimal current sensitivity and signal-to-noise ratio (SNR) for current-mode Hall devices. The conformal mapping calculation is performed study influence of device on SNR cross-like plates. indicates that plate can achieve in length-to-width (L/W) range 0.4-0.5 when thermal noise taken into account. Three-dimensional (3D) technology computer aided design (TCAD) simulation validates accuracy model. proposed...
Device physics and integrated device circuit simulation of "dual carrier field effect transistor" (DCFET) with effective channel length 5-30nm had been presented in C. Huang et al. (2004). Two dimensional approximation methods used these studies. Recently, two exact numerical simulations carried out for mesa type SOI switching "vertical dual (VDCFET). This method is this paper briefly. More details are reported R. Yang The comparison the results approximate physical shall be discussed shown...
This paper presents a novel time-to-amplitude converter (TAC) for single-photon direct timeof-flight (d-TOF) measurement. An innovative high impedance switch approach is proposed to significantly improve the stability of integral current and increase swing timing voltage, enabling linearity together with low power consumption on TAC. Implemented in standard 0.18 μm CMOS technology, TAC occupies only an area 100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
An advanced tunnel oxide layer process for 65 nm NOR-type floating-gate flash memory is proposed to improve quality by an additive sacrificial growth. The effectively controls the thickness variation of and improves flatness SiO2/Si interface across active area. traps' generation during program/erase cycling cells found be reduced, reliability property significantly improved as compared without process. technology applicable further scaled memories.
We have discovered and studied a new mode of operation transistors integrated circuits-dual carrier field effect (DCFETs) circuits (DCFEICs). In this paper we present the device physics theory some DC measurement results one type structure for our operation. show that, with mature SOI technology, lateral DCFET (LDCFET) is predicted to better performance than MOSFET. With proper design, cutoff frequency can be as high 6000 GHz an effective channel length 0.0368 /spl mu/m good microwave performance.
Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore possibility of improving SEU (single event upset) immunity SRAM cells. It is found. that capacitances both n/sup +//p-well p/sup +//n-well can vary in a wide range. The resulting FIT (failure time) rate shows significant reduction. HSPICE simulation indicates critical charge cell increases 5%. reduction funnel length due higher doping concentration source/drain area also...
A novel Hall dynamic offset cancellation circuit based on four-phase spinning current technique is introduced. The of sensor applies a configuration including modulator, instrumentation amplifier, correlated double sampling demodulator and adder, which effectively eliminate the 1/f noise, linearly amplify signal. Designed in 0.8 μm high voltage CMOS technology, simulation results show residual lower than 0.2 mT linearity up to 99.9%.