A5029806914- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- Advancements in PLL and VCO Technologies
- CCD and CMOS Imaging Sensors
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- Organic Electronics and Photovoltaics
- Advanced Neural Network Applications
- Ferroelectric and Negative Capacitance Devices
- Conducting polymers and applications
- Advanced MEMS and NEMS Technologies
- Mechanical and Optical Resonators
- Advanced Sensor and Energy Harvesting Materials
- Acoustic Wave Resonator Technologies
- Neuroscience and Neural Engineering
- Neural Networks and Applications
- Photonic and Optical Devices
- Sensor Technology and Measurement Systems
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Advanced biosensing and bioanalysis techniques
- Analytical Chemistry and Sensors
- VLSI and FPGA Design Techniques
University of Hawaiʻi at Mānoa
2024-2025
University of Hawaii System
2023-2025
Stanford University
2015-2024
Honolulu University
2024
University of Hawaii–West Oahu
2024
Palo Alto University
2023
Georgia Institute of Technology
2021
Neurosciences Institute
2020
Xilinx (United States)
2019
University of Michigan
2019
Previous breakthroughs in stretchable electronics stem from strain engineering and nanocomposite approaches. Routes toward intrinsically molecular materials remain scarce but, if successful, will enable simpler fabrication processes, such as direct printing coating, mechanically robust devices, more intimate contact with objects. We report a highly conducting polymer, realized range of enhancers that serve dual function: (i) they change morphology (ii) act conductivity-enhancing dopants...
Soft and conformable wearable electronics require stretchable semiconductors, but existing ones typically sacrifice charge transport mobility to achieve stretchability. We explore a concept based on the nanoconfinement of polymers substantially improve stretchability polymer without affecting mobility. The increased chain dynamics under significantly reduces modulus conjugated largely delays onset crack formation strain. As result, our fabricated semiconducting film can be stretched up 100%...
Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision by simple power-efficient open-loop stages. In multibit first stage of 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier savings over conventional implementation. The ADC has been fabricated 0.35-μm double-poly quadruple-metal CMOS...
Recent advances in convolutional neural networks have considered model complexity and hardware efficiency to enable deployment onto embedded systems mobile devices. For example, it is now well-known that the arithmetic operations of deep can be encoded down 8-bit fixed-point without significant deterioration performance. However, further reduction precision as low 3-bit results losses In this paper we propose a new data representation enables state-of-the-art 3 bits with negligible loss...
This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, statistics-based background calibration scheme for timing skew is employed. The detected digital domain through correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset reduced foreground calibrated trim-DAC circuitry....
The trend of pushing deep learning from cloud to edge due concerns latency, bandwidth, and privacy has created demand for low-energy convolutional neural networks (CNNs). single-layer classifier in [1] achieves sub-nJ operation, but is limited moderate accuracy on low-complexity tasks (90% MNIST). Larger CNN chips provide dataflow computing high-complexity (AlexNet) at mJ energy [2], deployment remains a challenge off-chip DRAM access energy. This paper describes mixed-signal binary...
Electronic biosensors are a natural fit for field-deployable diagnostic devices because they can be miniaturized, mass produced, and integrated with circuitry. Unfortunately, progress in the development of such platforms has been hindered by fact that mobile ions present biological samples screen charges from target molecule, greatly reducing sensor sensitivity. Under physiological conditions, thickness resulting electric double layer is less than 1 nm, it generally assumed electronic...
This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over past eleven years indicates that power efficiency ADCs has improved on average by a factor two every years. A closer inspection impact technology scaling is presented to explain observed trend context shrinking supply voltages and increasing device speed. Finally, discussion minimalistic digitally assisted design approaches used sketch route toward further improvements ADC performance.
A power and area efficient sensor interface consumes 6.4 mW from 1.2 V while occupying 5 mm × in 0.13 μm CMOS. The offers simultaneous access to 96 channels of broadband neural data acquired cortical microelectrodes as part a head-mounted wireless recording system, enabling basic neuroscience well neuroprosthetics research. Signals are conditioned with front-end achieving 2.2 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub>...
This brief analyzes the effect of load capacitor mismatch on offset a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in typical 0.18-mum CMOS latch, capacitive imbalance only 1 fF can lead to offsets several tens millivolts
The trend of pushing inference from cloud to edge due concerns latency, bandwidth, and privacy has created demand for energy-efficient neural network hardware. This paper presents a mixed-signal binary convolutional (CNN) processor always-on applications that achieves 3.8 μJ/classification at 86% accuracy on the CIFAR-10 image classification data set. goal this is establish minimum-energy point representative task, using available design tradeoffs. BinaryNet algorithm training networks with...
A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the ADCs, based on first principles and using pipeline flash architectures as examples. We find that high-resolution ADCs by noise, whereas technology limiting factor low-resolution devices. Our model assumes use digital error correction, but also study...
We present the concept of logarithmic computation for neural networks. explore how encoding non-uniformly distributed weights and activations is preferred over linear at resolutions 4 bits less. Logarithmic enables networks to 1) achieve higher classification accuracies than fixed-point low 2) eliminate bulky digital multipliers. demonstrate our ideas in hardware realization, LogNet, an inference engine using only bitshift-add convolutions across computing fabric. The opportunities from work...
This paper introduces BinarEye: the first digital processor for always-on Binary Convolutional Neural Networks. The chip maximizes data reuse through a Neuron Array exploiting local weight Flip-Flops. It stores full network models and feature maps hence requires no off-chip bandwidth, which leads to 230 lb-TOPS/W peak efficiency. Its 3-levels of flexibility - (a) reconfiguration, (b) programmable depth (c) width allow trading energy accuracy depending on task's requirements. BinarEye's...
This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring dedicated signal conditioning and delta-sigma modulation integrated within area of 250 µm by µm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, interfaces to 4 × subarray capacitive micromachined ultrasound transducers (CMUTs). front-end each employs coarse/fine gain tuning architecture fulfill the 90-dB dynamic...
Abstract Printable elastic conductors open up new opportunities in large‐area fabrication of wearable electronics and prosthetics. Furthermore, they have the potential to advance health monitoring continuous diagnostics by implementing sensor arrays close proximity skin. Such devices need be comfortable wear must accommodate strains deformations such as twisting stretching. A conductive polymer ink for interconnects electrodes is introduced. The processability inkjet printing enables...
Modern deep neural networks (DNNs) require billions of multiply-accumulate operations per inference. Given that these computations demand relatively low precision, it is feasible to consider analog computing, which can be more efficient than digital in the low-SNR regime. This overview article investigates potential mixed analog/digital computing approaches context modern DNN processor architectures, are typically limited by memory access. We discuss how memory-like and in-memory compute...