Reservoir computing systems utilize dynamic reservoirs having short-term memory to project features from the temporal inputs into a high-dimensional feature space. A readout function layer can then effectively analyze projected for tasks, such as classification and time-series analysis. The system efficiently compute complex data with low-training cost, since only needs be trained. Here we experimentally implement reservoir using memristor array. We show that internal ionic processes of...

In this paper, we investigate the read operation of memristor-based memories. We analyze sneak paths problem and provide a noise margin metric to compare various solutions proposed in literature. also power consumption associated with these solutions. Moreover, study effect aspect ratio memory array on paths. Finally, introduce new technique for solving by gating cell using three-terminal memistor device.

A flexible version of traditional thin lead zirconium titanate ((Pb 1.1 Zr 0.48 Ti 0.52 O 3 )‐(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in arena. The PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol‐gel coating cycles required (i.e., more cost‐effective), and, fabrication wise, is suitable for further scaling lateral dimensions nano‐scale due larger feature size‐to‐depth aspect ratio (critical...

Neuromorphic systems using memristors as artificial synapses have attracted broad interest for energy-efficient computing applications. However, networks based on these purely passive devices can be affected by parasitic effects such series resistance and sneak path problems. Here, we analyze the of factors performance memristor-based neuromorphic systems. During vector-array multiplication, line cause significant distortion output current activity corresponding neurons. An approach to...

Since the fourth fundamental element (Memristor) became a reality by HP labs, and due to its huge potential, mathematical models necessity. In this paper, we provide simple model of Memristors characterized linear dopant drift for sinusoidal input voltage, showing high matching with nonlinear SPICE simulations. The frequency response Memristor's resistance bounding conditions are derived. fundamentals pinched i-v hysteresis, such as critical resistances, hysteresis power maximum operating...

In this paper mathematical models of the HP Memristor for DC and periodic signal inputs are provided.The need a rigid model using conventional current voltage quantities is essential development many promising Memristors' applications.Unlike previous works, which focuses on sinusoidal input waveform, we derived rules any signals in general terms current.Square triangle waveforms studied explicitly, extending formulas square wave.The limiting conditions saturation also provided case either or...

In this paper, we introduce for the first time, a closed-form solution memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates effect of by reading stored data multiple access points and evaluating simple addition/subtraction on different readings. new method requires fewer steps compared to previously reported techniques, has very small impact density. To verify underlying theory, proposed system is simulated Synopsys HSPICE showing...

SUMMARY In this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed require no reactive components, that is, inductors or capacitors, rather, ‘resistance storage’ property memristor is exploited to generate oscillation. Different types MRLO are presented, and each type, closed form expressions derived oscillation condition, frequency, range Derived equations further verified using transient circuit simulations. A comparison...

In this paper, a new controllable V-shape multiscroll attractor is presented, where variety of symmetrical and unsymmetrical attractors with variable number scrolls can be controlled using staircase nonlinear function the parameters system. This used to generate random signals symbol distribution. Digital implementation proposed generator also presented Xilinx Virtex ® 4 Field Programmable Gate Array experimental results are provided. The digital realization easily fits into small area...

The first reactance-less oscillator is introduced. By using a memristor, the can be fully implemented on-chip without need for any capacitors or inductors, which results in an area-efficient integrated solution. concept of operation proposed explained and detailed mathematical analysis Closed-form expressions oscillation frequency conditions are derived. Finally, derived equations verified with circuit simulations showing excellent agreement.

High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure both its principal advantage and source undesired sneak-paths current. This parasitic current could consume an enormous amount energy ruin readout process. We introduce new adaptive-threshold techniques that utilize locality hierarchy properties computer-memory system to address problem. proposed methods require single memory access per...

Simulated annealing (SA) was successfully implemented and accelerated by in-memory computing hardware/software package using RRAM crossbar arrays to solve a spin glass problem. Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> -based array stochastic Cu-based CBRAM devices were utilized for calculation of the Hamiltonian decision spin-flip events, respectively. A parallel strategy...

In this paper, we present a fully digital differential chaos based random number generator. The output of the circuit is proved to be chaotic by calculating time series maximum Lyapunov exponent. We introduce new post processing technique improve distribution and statistical properties generated data. post-processed passes NIST Sp. 800-22 tests. system written in Verilog VHDL realized on Xilinx Virtex <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this paper, we study the effect of numerical solution accuracy on digital implementation differential chaos generators. Four systems are built a Xilinx Virtex 4 FPGA using Euler, mid-point, and Runge-Kutta fourth order techniques. The twelve implementations compared based used area, maximum throughput, Lyapunov exponent, autocorrelation confidence region. Based circuit performance chaotic response different implementations, it was found that less complicated has better higher throughput.

For decades, advances in electronics were directly driven by the scaling of CMOS transistors according to Moore's law. However, both and classical computer architecture are approaching fundamental practical limits, new computing architectures based on emerging devices, such as resistive random-access memory (RRAM) expected sustain exponential growth capability. Here, we propose a novel memory-centric, reconfigurable, general purpose platform that is capable handling explosive amount data...

Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage ruins memory readout process for arrays, and analyze tradeoff between array density its power consumption. We propose a novel technique underlying circuitry, which able to compensate transistor leakage-current effect in gated array.

Utilizing internal dynamic processes in memristors may allow the devices to process temporal data natively. In this letter, we show ability of second-order information time domain, and discuss a memristive STDP network that can learn classify as well classical patterns.

This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using Euler approximation. The digitization approach enables controllable that reliably provide sinusoidal or output on a selection input. New are introduced, derived logical and arithmetic operations between two system bus widths, with up to 100× higher maximum Lyapunov exponent than original systems. resulting is shown pass NIST SP. 800-22 statistical test suite...

To address the von Neumann bottleneck that leads to both energy and speed degradations, in-memory processing architectures have been proposed as a promising alternative for future computing applications. In this paper, we present an system based on resistive random-access memory (RRAM) crossbar arrays is reconfigurable can potentially perform parallel general tasks. The consists of small look-up tables (LUTs), block, two search auxiliary blocks, all implemented in same RRAM array. External...

This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width 12-bits for reliable behavior is observed, below which system output becomes periodic. Beyond this threshold, maximum Lyapunov exponent (MLE) shown to improve up peak value at 16-bits and subsequently decrease increasing width. The MLE also gradually increase number introduced internal delay cycles until 14 cycles, after loses properties....

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge building devices on structurally foldable platform high integration density. present a CMOS compatible process to demonstrate for first time memristive fabricated bulk monocrystalline silicon (100) which is next transformed into flexible thin sheet fabric all pre-fabricated devices. This preserves ultra-high density advantage unachievable other substrates. In...