A5032850366- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Neural dynamics and brain function
- Neural Networks and Applications
- Interconnection Networks and Systems
- Computational Geometry and Mesh Generation
- Magnetic properties of thin films
- CCD and CMOS Imaging Sensors
- Neural Networks and Reservoir Computing
- Parallel Computing and Optimization Techniques
- 3D IC and TSV technologies
- Neuroscience and Neural Engineering
- Distributed systems and fault tolerance
- Advanced Data Storage Technologies
- Digital Image Processing Techniques
- Carbon Nanotubes in Composites
- Mechanical and Optical Resonators
- VLSI and FPGA Design Techniques
- 3D Modeling in Geospatial Applications
- Advanced Numerical Analysis Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Manufacturing Process and Optimization
- Machine Learning and ELM
- Advancements in Photolithography Techniques
Toshiba (Japan)
2014-2024
Tokyo Institute of Technology
2001-2009
Mie University
1995
In this paper, the progress of P-MTJs is reviewed and prospects for normally-off memory hierarchy based on new results are discussed.
We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low are adapting run time gating architecture (shown in Fig. 1), and satisfying both fast low-power writing, namely, 3 nsec 0.09 pJ, p-MTJ cell 3). As shown Table 1, only our developed has achieved nsec, pJ. Thanks to p-MTJ, cache memory could be reduced over 80% without degradation performance.
This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic junction (MTJ) spin manipulation technologies such as spin-transfer torque (STT) magnetoresistive random access memory (MRAM). Major challenges ultrahigh-density STT-MRAM with perpendicular magnetization novel functional devices related to MRAM are discussed.
Abstract Learning is a fundamental component of creating intelligent machines. Biological intelligence orchestrates synaptic and neuronal learning at multiple time scales to self-organize populations neurons for solving complex tasks. Inspired by this, we design experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN) . MEMSORN incorporates resistive memory (RRAM) in its synapses which configure their state based on...
This paper presents novel processor architecture for HP-processor with MRAM/SRAM-based hybrid cache memory. By simulations of using MTJs, it has been clarified that total power the perpendicular-(p-)STT-MRAM [H. Yoda, et al., Current Appl. Phys. 10, e87 (2010)] can be reduced by 50.2% without any degradation operation speed. is first report on effectively decreasing HP-processors no performance magnetic The presented will step to realize next generation “normally-off computers.”
We have proposed 3 nanoarchitectures with carbon nanotube-based nano-electromechanical systems (CNT-NEMS) switch a floating gate. It is shown that logic based on them has the potential to replace CMOS using process technology of less than 45 nm. Furthermore, CNT-NEMS-based 3-D circuits realize extremely high bandwidth over 10 petabyte/s very low latency several ps. The most effective applications are 3D on-chip crossbar bus and future network, which will largely determine performance...
To reduce power consumption of CPU, nonvolatile cache memory has been expected by replacing conventional volatile based on SRAM. This paper describes hierarchy design using fast and low-power perpendicular (FL-p-) STT-MRAM. For L3, L2 L1 cache, 1T-1MTJ with FL-p-STT-MRAM, 6T-2MTJ, short write pulse 6T-2MTJ having voltage-induced magnetization switching presented for the most suitable combination memory.
Lithium (Li)-ion materials such as LiCoO2 and (Li3PO4)-N (LiPON) are used in Li-ion all-solid-state batteries, now expected to be ion-electron hybrid create a new degree of freedom future integrated circuits. We fabricated thin-film devices on the basis LiCoO2/LiPON/Cu ultrathin titanium oxide (TiOx) demonstrate their type resistance change mechanism characteristics. Multi-level changes promising synaptic plasticity were obtained, properties enable neuromorphic computing enter era.
Spiking randomly connected neural network (RNN) hardware is promising as ultimately low power devices for temporal data processing at the edge. Although potential of RNNs has been demonstrated, randomness architecture often causes performance degradation. To mitigate such degradation, self-organization mechanism using intrinsic plasticity (IP) and synaptic (SP) should be implemented in spiking RNN. Therefore, we propose hardware-oriented models these functions. implement function IP, a...
Magnetic RAM (MRAM) has a unique potential to change its memory capacity from small large capacity. This paper presents novel variable circuit based on 1T-1MTJ of perpendicular STT-MRAM arrays. It can cover all hierarchy and computing units that are adjustable applications by selecting single, dual or quadruple cell mode changing resources.
This paper presents fast and low-power embedded nonvolatile memory technologies circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.
Three-dimensional integrated circuits (3D-IC) have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design analysis of 3D-IC technologies based on accurate calculation interconnects delays using 16-core processors as case studies. Performance improvement vs. 2D-IC is increased scales down, which consistent with expected trend. The over 20%. Furthermore, 65 nm (or 45 nm) technology superior that 32 technology....
In conclusion, e-STT-MRAM is thus expected to play much important and valuable role for wide range ICT applications. To increase those markets long term, scalable MTJ technologies co-optimization of technology, circuit systems should be continuously developed long-term reliable secure services.
Artificial neural network (NN) circuits are proposed and analyzed from the viewpoints of flexibility robustness based on memristive devices. The typical 3-layered fully-connected NN is a primitive unit Deep Learning (DL) plays key role in determining DL performance. We propose three types structure at circuit level - fully-digital, analog/digital mixed, fully-analog focusing digital or analog calculations such as multiplier accumulator, examine their figures merit. One property...
This paper presents novel processor architecture for HP-processor with nonvolatile/volatile hybrid cache memory. By simulations of high-performance (HP)-processor using MTJs, it has been clarified that total power the perpendicular-(p-)STT-MRAM can be reduced by over 90 % little degradation performance. The presented nonvolatile memory hierarchy will realize "normally-off computers".
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked structure consisting a small sense amplifier shared few 3D cells has been presented. The 16bit TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> chip was fabricated and demonstrated. estimated per unit in sub-65nm CMOS technology indicates that potential to achieve ultra-high required for future processors.
This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active is intermittent refresh process DRAM-mode. D-MRAM has advantage static consumptions compared conventional SRAM, because there are no leakage paths in cell and it not needed supply voltage its cells when used as MRAM-mode....
This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active is intermittent refresh process DRAM-mode. D-MRAM has advantage static consumptions compared conventional SRAM, because there are no leakage paths in cell and it not needed supply voltage its cells when used as MRAM-mode....
This paper describes state-of-the-art STT-MRAM, which can drastically save energy consumption dissipated in cache memory system compared with conventional SRAM-based ones. also presents how to build hierarchy both the state-of-art STT-MRAM and SRAM reduce consumption. The key point is "break-even-time aware design" based on normally-off operation. For further power reduction, an intelligent management technique for STT-MRAM-based discussed.
Abstract Spike timing-dependent plasticity (STDP), which is widely studied as a fundamental synaptic update rule for neuromorphic hardware, requires precise control of continuous weights. From the viewpoint hardware implementation, simplified desirable. Although STDP with stochastic binary synapses was proposed previously, we find that it leads to degradation memory maintenance during learning, unfavourable unsupervised online learning. In this work, propose model where cumulative...
We propose a 3D architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire for future networks-on-chip (NoC). Based on new architecture, extremely high bandwidth with very low latency can be realized. These promising features are useful NoCs
Recent progress of through-silicon-via (TSV) process is so impressive that everyone can expect real 3D-IC era. The most valuable advantages decreasing interconnects. Although analysis this has been reported in some specific case study, the general theory for quantitative not studied. In cases, advantage overestimated and much different from chip designs expected. This paper presents qualitative design especially sub-65nm CMOS generation designers' point view. What understood how important...