A5101657612- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- MXene and MAX Phase Materials
- Nanowire Synthesis and Applications
- Thin-Film Transistor Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- GaN-based semiconductor devices and materials
- Advanced MEMS and NEMS Technologies
- Silicon Nanostructures and Photoluminescence
- Chalcogenide Semiconductor Thin Films
- Advanced Memory and Neural Computing
- Mechanical and Optical Resonators
- Ga2O3 and related materials
- Acoustic Wave Resonator Technologies
National Yang Ming Chiao Tung University
1998-2023
Lehigh University
2013
Rutgers, The State University of New Jersey
1982
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3 × 9 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit remarkable I <sub xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -I...
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because difference size curvature between planar TG or GAA structures. Because...
We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain gate-stack thermal budget and 2) adopting high-k metal gate low-temperature process realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within same footprint without degrading performance is demonstrated. Series resistance limit pointed out bottle neck for increment with...
This paper analyzes the dielectric charging effects in microelectromechanical capacitive switches with dielectric-dielectric contacts. Measurements were performed on different contact topologies to characterize of surface and bulk under hold-down voltages periods. The results showed a strong correlation between treatment as well area. With proper bumps, was suppressed remaining sufficiently small allow withstand long-term tests.
We have experimentally demonstrated fully suspended nanowire (NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm × 12.5-nm); they exhibit a remarkable I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -I xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of over 10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> . This work, for the first time,...
The electron diffusion lengths in liquid-phase epitaxial (LPE) p-GaAs:Ge layers were determined by using the electron-beam-induced current method. length is found to reduce gradually as doping level of layer increased. For four LPE with carrier concentration 1.4×1016 cm−3, 2.0×1017 1.3×1018 and 2.5×1019 be 8.1, 6.7, 5.1, 1.2 μm, respectively.
In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices RTA exhibit superior electrical characteristics to those owing better crystallinity. The crystallinity of the device results from larger grain size fewer defects, leading higher field-effect mobility μFE compared devices RTA. p-type double layer poly-Si FETs show...
This work reports a comprehensive investigation on the negative-capacitance (NC) related ferroelectric FET (FE-FET) with Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Zr xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) different sweeping sequences. Devices of planar capacitor and Gate-All-Around (GAA) 5.3 × 9 nm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...
One-time programmable (OTP) memory is essential to the security and gaming industries because of its "write once, read many" capability. This device supports N-metal–oxide–semiconductor polycrystalline-silicon junctionless gate-all-around (GAA) nanowire transistor technology can perform multistate antifuse. It capable functioning in four states instead standard two (open/short). Furthermore, be as fully open (0, 0), drain–gate breakdown 1), source–gate (1, full 1) states. The antifuse formed...
In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n± active device layer, are successfully demonstrated to show better performance compared with conventional nanosheet (NS) JLTs. Because the potential barrier between n-channel and p-body in VC-JLT can be controlled by gate, effective conduction channel behaves as “variable” channel, thickness is thinner or thicker than physical n <sup...
In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, crystallinity of channels can be modified easily changing thickness layer. The better devices with 60 nm top attributed to larger average grain size and fewer defects, leading higher field-effect carrier mobility compared 40 80 layer devices. Both n-type p-type exhibit superior electrical...
In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results, particularly when utilized as transistor channels for computing applications. However, intricate nature assembly winding commensurate currents hinder standard modeling. Inspired by quantum collapse states information decoding in implementation analogous path to facilitate detection circuits modifying their network topology is explored....
Poly-Si GAA FETs using sidewall damascened method are successfully demonstrated. By manipulating the stress imposed by nitride layer, crystallinity of poly-Si can be modified changing thickness top nitride. Devices with larger grain size and fewer defects lead to superior electrical characteristics. Hot carrier gate reliability devices were then investigated. With better crystallinity, characteristics degrade less under hot due electric field enhancement. On contrary, degradation is...