A5100343643- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- VLSI and FPGA Design Techniques
- Speech Recognition and Synthesis
- Speech and Audio Processing
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Lasers and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in PLL and VCO Technologies
- Low-power high-performance VLSI design
- UAV Applications and Optimization
- Airway Management and Intubation Techniques
- Aerodynamics and Fluid Dynamics Research
- Natural Language Processing Techniques
- Neural dynamics and brain function
- Electromagnetic Compatibility and Noise Suppression
- IPv6, Mobility, Handover, Networks, Security
- 3D IC and TSV technologies
- Privacy-Preserving Technologies in Data
- Advanced Wireless Communication Technologies
- Advanced Data Storage Technologies
- Telecommunications and Broadcasting Technologies
- Metal and Thin Film Mechanics
Korea Advanced Institute of Science and Technology
2008-2024
Ulsan National Institute of Science and Technology
2023
Daegu Gyeongbuk Institute of Science and Technology
2019-2022
University of Minnesota
2018-2021
Samsung (South Korea)
2013-2021
SK Group (South Korea)
2021
University of Minnesota System
2019
Daejeon Institute of Science and Technology
2009
Visual Speech Recognition (VSR) aims to infer speech into text depending on lip movements alone. As it focuses visual information model the speech, its performance is inherently sensitive personal appearances and movements, this makes VSR models show degraded when they are applied unseen speakers. In paper, remedy degradation of speakers, we propose prompt tuning methods Deep Neural Networks (DNNs) for speaker-adaptive VSR. Specifically, motivated by recent advances in Natural Language...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit main processor, 8 single-instruction multiple-data (SIMD) clusters processing elements in each cluster, a cellular neural network engine (VAE), matching accelerator, and DMA-like external interface. The VAE 2-D shift...
A neural network hardware inspired by the 3-D NAND flash array structure was experimentally demonstrated in a standard 65-nm CMOS process. Logic-compatible embedded memory cells were used for storing multi-level synaptic weights while bit-serial architecture enables 8 bit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> multiply-and-accumulate operation. novel...
We report the feasibility of ultralow- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> amorphous boron nitride ( notation="LaTeX">$\alpha $ -BN) film as a new capping layer for copper (Cu) interconnects. -BN thin films were successfully deposited using plasma-enhanced chemical vapor deposition (PECVD) process. The CVD-grown showed -value low 2.0 at 3 nm thickness, leakage...
Multimodal large language models (MLLMs) have recently become a focal point of research due to their formidable multimodal understanding capabilities. For example, in the audio and speech domains, an LLM can be equipped with (automatic) recognition (ASR) abilities by just concatenating tokens, computed encoder, text tokens achieve state-of-the-art results. On contrary, tasks like visual audio-visual (VSR/AVSR), which also exploit noise-invariant lip movement information, received little or...
The visual attention engine (VAE), an 80 times 60 digital cellular neural network, rapidly extracts global features used as attentional cues to streamline detailed object recognition. A peak performance of 24 GOPS is achieved by 120 processing elements (PE) shared the cells. 2D shift register based data transactions enable 93% PE utilization. Integrated within recognition SoC, 4.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> VAE...
In this paper, we present a counter based measurement circuit for in-situ characterization of analog-to-digital converter (ADC) differential non-linearity (DNL) and integral (INL). An array counters collects the histogram ADC output code triangular input voltage. Since operation data transfer are separated in time, DNL INL results immune to noise setup. Using proposed method, studied short-term bias temperature instability (BTI) effects successive-approximate-register under different...
Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and enable signals are presented. The proposed scheme enables the reduction of data-to-output delay elimination MUX-scan logic from setup time path flip-flop, at cost small power overhead. comparison results using 45 nm CMOS process indicate that worst-case DQ flip-flop is reduced up to 59% while energy-delay product improved 80% compared conventional master-slave flip-flop. silicon show new...
<p>We propose a visual programming framework that helps designer easily convert an existing analog layout into the generator. Using graphical user interface (GUI), designers can load layout, it generator, and visually verify generated result. A GUI-supported method enables intuitive straightforward to significantly reduce required skills coding workload. Through program blocks, describe compile Layout-code synchronization updates blocks automatically when elements are created, edited,...
In this paper, we present DevFormer, a novel transformer-based architecture for addressing the complex and computationally demanding problem of hardware design optimization. Despite demonstrated efficacy transformers in domains including natural language processing computer vision, their use has been limited by scarcity offline data. Our approach addresses limitation introducing strong inductive biases such as relative positional embeddings action-permutation symmetricity that effectively...
In recent years, blockchain technology has been frequently exploited to address new security requirements for unmanned aerial vehicle (UAV)-assisted data collection (U-DC). However, the latency commit ledger emerged as a issue. this paper, therefore, we analyze timely update probability (TUP) of ledger, which is that collected from UAV updated in within given target latency. For analysis, first define TUP U-DC networks, using both communication and latencies. We then derive closed-form...
Using simple on-chip monitoring circuits, we precisely characterized the impact of hot carrier injection and bias temperature instability on frequency phase noise degradation a 65nm all-digital PLL circuit. Experimental data shows that degrades with aging even though output is maintained constant due to feedback operation. Results show applying high annealing can recover most degradation.
In the Internet of Things (IoT) era, data movement between processing units and memory is a critical factor in overall system performance. Processing-in-Memory (PIM) promising solution to address this bandwidth bottleneck by performing portion computation inside memory. Many prior studies have enabled various PIM operations on nonvolatile (NVM) modifying sense amplifiers (SA). They exploit single amplifier handle multiple bitlines with multiplexer (MUX) since SA circuit takes much larger...
좌상엽 절제술은 폐엽 중 가장 큰 엽을 절제하는 수술이다. 수술 후 남아있는 폐가 팽창을 하면서 기관지의 형상 변화를 유도한다. 기관지, 폐동맥, 폐정맥 등을 덮고 있는 것을 폐 인대라고 한다. 방법으로는 인대를 박리하는 방법과 보존하는 방법이 있다. 본 연구에서는 절제술 시 폐인대를 박리한 환자의 CT 이미지로부터 전과 후의 기관지 데이터를 분석하였다. 모델을 단순화하여 전산유체역학 해석을 통해 요인에 따른 기류의 평가하였다. 길이, 곡률, 단면적에서 형상의 보였으며, 이 세 요인을 가지고 일정한 변화량을 주어 모델링하여 시뮬레이션 한 결과 단면적 변화가 기류에 영향을 미치는 확인하였다. 단면 내경이 0.5배로 감소하는 경우 체적 유량이 약 64%
<p>We propose a visual programming framework that helps designer easily convert an existing analog layout into the generator. Using graphical user interface (GUI), designers can load layout, it generator, and visually verify generated result. A GUI-supported method enables intuitive straightforward to significantly reduce required skills coding workload. Through program blocks, describe compile Layout-code synchronization updates blocks automatically when elements are created, edited,...
<p>We propose a visual programming framework that helps designer easily convert an existing analog layout into the generator. Using graphical user interface (GUI), designers can load layout, it generator, and visually verify generated result. A GUI-supported method enables intuitive straightforward to significantly reduce required skills coding workload. Through program blocks, describe compile Layout-code synchronization updates blocks automatically when elements are created, edited,...
In this article, for the first time, we propose a transformer network-based reinforcement learning (RL) method power distribution network (PDN) optimization of high bandwidth memory (HBM). The proposed can provide an optimal decoupling capacitor (decap) design to maximize reduction PDN self- and transfer impedance seen at multiple ports. An attention-based is implemented directly parameterize decap policy. optimality performance significantly improved since attention mechanism has powerful...