A5040354801- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Data Storage Technologies
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Silicon Carbide Semiconductor Technologies
- Advanced biosensing and bioanalysis techniques
- Nanoparticles: synthesis and applications
- Thin-Film Transistor Technologies
- Semiconductor materials and interfaces
- Radio Frequency Integrated Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Antimicrobial agents and applications
- 3D IC and TSV technologies
- Lipid Membrane Structure and Behavior
- Biosensors and Analytical Detection
- Wound Healing and Treatments
Kaohsiung Medical University
2024
Intel (United States)
1989-2015
Taiwan Semiconductor Manufacturing Company (United States)
2010
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products the first time. Low standby and high voltage transistors exploiting superior short channel control, < 65mV/dec subthreshold slope <40mV DIBL, of Tri-Gate architecture have fabricated concurrently with speed logic in a single chip to achieve industry drive currents at record leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um 30pA/um Ioff, 0.75V, were used build 380Mb SRAM capable operating 2.6GHz...
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P I<inf>on</inf> values of 1200/1100 µA/µm for I<inf>off</inf>=100nA/µm at 1V. Excellent device electrostatic control is demonstrated gate length (L<inf>gate</inf>) down to 20nm. Dual-Epitaxy and multiple stressors are essential boost performance. Dual workfunction (WF) with an advanced High-K/Metal (HK/MG) stack deployed in integration-friendly process flow. This dual-WF approach provides excellent...
A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, noise mitigation options. The low leakage the high-k dielectric enables triple architecture support ultra high voltage tolerant I/O devices concurrently. Embedded memories include density (0.148...
The urbanization process is unstoppable, with towering high-rise buildings emerging one after another. In this rapidly developing era, urban continue to rise, and the safety hazards fire problems of in cities have not been well solved. Intelligent smoke alarms based on microcontrollers significant practical significance. Design a real-time detection system STM32 microcontroller as core, combined temperature, smoke, flame sensors detect various environmental values real time, providing early...
A leading edge 14 nm SoC platform technology based upon the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation Tri-Gate transistor [5] has been optimized for density, low power and wide dynamic range. 70 gate pitch, 52 metal pitch 0.0499 um xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> HDC SRAM cells are most aggressive design rules reported 14/16 node process to achieve Moore's Law 2x density scaling over 22 node. High...
Nonantibiotic approaches must be developed to kill pathogenic bacteria and ensure that clinicians have a means treat wounds are infected by multidrug-resistant bacteria. This study prepared matchstick-like Ag2S–ZnS heteronanostructures (HNSs). Their hydrophobic surfactants were then replaced with hydrophilic poly(ethylene glycol) (PEG) thioglycolic acid (TGA) through the ligand exchange method, this was followed ascorbic (AA) conjugation TGA esterification, yielding well-dispersed PEGylated...
Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from 1.0- mu m EPROM-base technology, 15.2- m/sup single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent area required by previous 1.5- device. One most significant aspects this is one-million erase/program cycle capability. The exhibits 90-ns read access time while reprogramming gives 900-ms array erase 10- s/byte programming...
A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have achieved at 1.1 V and off-state leakage 1 nA/um. Record RF performance a mainstream 45nm bulk with measured f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> /f...
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices high performance and very low leakage to address advanced RF/mobile communications markets. NMOS achieves an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 420GHz. Concurrently, a 30pA/um 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier...
An electrically erasable, reprogrammable, 90-ns 1-Mb flash memory capable of greater than 100000 erase/program cycles is described. The implements a command port and an internal reference voltage generator, allowing microprocessor-controlled reprogramming. access time results from the 95- mu A cell current, low resistance polysilicide word lines, advanced scaled periphery transistors, di/dt optimized data-out buffer. Using CMOS inputs, power dissipation 40 mW in active state 20 W standby....